Concurrency-oriented optimization for low-power asynchronous systems. - Luis A. Plana; Steven M. Nowick (ISLPED, 1996)

Pulse-mode macromodular systems. - Luis A. Plana; Stephen H. Unger (ICCD, 1998)

Architectural optimization for low-power nonpipelined asynchronous systems. - Luis A. Plana; Steven M. Nowick (IEEE Trans. Very Large Scale Integr. Syst., 1998)

SPA - A Synthesisable Amulet Core for Smartcard pplications. - W. J. Bainbridge; Andrew Bardsley; Steve Temple; Jim D. Garside; Peter A. Riocreux; Luis A. Plana (ASYNC, 2002)

An Investigation into the Security of Self-Timed Circuits. - Z. C. Yu; Stephen B. Furber; Luis A. Plana (ASYNC, 2003)

SPA - a secure Amulet core for smartcard applications. - Luis A. Plana; Peter A. Riocreux; W. J. Bainbridge; Andrew Bardsley; Steve Temple; Jim D. Garside; Z. C. Yu (Microprocess. Microsystems, 2003)

The Design and Test of a Smartcard Chip Using a CHAIN Self-Timed Network-on-Chip. - W. J. Bainbridge; Luis A. Plana; Stephen B. Furber (DATE, 2004)

Attacking Control Overhead to Improve Synthesised Asynchronous Circuit Performance. - Luis A. Plana; Sam Taylor; Doug A. Edwards (ICCD, 2005)

Performance-driven syntax-directed synthesis of asynchronous processors. - Luis A. Plana; Doug A. Edwards; Sam Taylor; Luis A. Tarazona; Andrew Bardsley (CASES, 2007)

A GALS Infrastructure for a Massively Parallel Multiprocessor. - Luis A. Plana; Stephen B. Furber; Steve Temple; Muhammad Mukaram Khan; Yebin Shi; Jian Wu; Shufan Yang (IEEE Des. Test Comput., 2007)

An admission control system for QoS provision on a best-effort GALS interconnect. - Shufan Yang; Steve B. Furber; Yebin Shi; Luis A. Plana (ACSD, 2008)

Automatic Compilation of Data-Driven Circuits. - Sam Taylor; Doug A. Edwards; Luis A. Plana (ASYNC, 2008)

SpiNNaker: The Design Automation Problem. - Andrew D. Brown; David R. Lester; Luis A. Plana; Steve B. Furber; Peter R. Wilson (ICONIP (2), 2008)

SpiNNaker: Mapping neural networks onto a massively-parallel chip multiprocessor. - Muhammad Mukaram Khan; David R. Lester; Luis A. Plana; Alexander D. Rast; Xin Jin 003; Eustace Painkras; Stephen B. Furber (IJCNN, 2008)

An On-Chip and Inter-Chip Communications Network for the SpiNNaker Massively-Parallel Neural Net Simulator. - Luis A. Plana; John Bainbridge; Steve B. Furber; Sean Salisbury; Yebin Shi; Jian Wu (NOCS, 2008)

Fault Tolerant Delay Insensitive Inter-chip Communication. - Yebin Shi; Steve B. Furber; Jim D. Garside; Luis A. Plana (ASYNC, 2009)

A Synthesisable Quasi-Delay Insensitive Result Forwarding Unit for an Asynchronous Processor. - Luis A. Tarazona; Doug A. Edwards; Luis A. Plana (DSD, 2009)

Understanding the interconnection network of SpiNNaker. - Javier Navaridas; Mikel Luján; José Miguel-Alonso; Luis A. Plana; Steve B. Furber (ICS, 2009)

A universal abstract-time platform for real-time neural networks. - Alexander D. Rast; Mukaram M. Khan; Xin Jin 003; Luis A. Plana; Steve B. Furber (IJCNN, 2009)

Event-Driven Configuration of a Neural Network CMP System over a Homogeneous Interconnect Fabric. - Muhammad Mukaram Khan; Javier Navaridas; Alexander D. Rast; Xin Jin 003; Luis A. Plana; Mikel Luján; John V. Woods; José Miguel-Alonso; Steve B. Furber (ISPDC, 2009)

Adaptive admission control on the SpiNNaker MPSoC. - Shufan Yang; Stephen B. Furber; Luis A. Plana (SoCC, 2009)

A Token-Managed Admission Control System for QoS Provision on a Best-Effort GALS Interconnect. - Shufan Yang; Stephen B. Furber; Yebin Shi; Luis A. Plana (Fundam. Informaticae, 2009)

A communication infrastructure for a million processor machine. - Andrew D. Brown; Steve B. Furber; Jeff S. Reeve; Peter R. Wilson; Mark Zwolinski; John E. Chad; Luis A. Plana; David R. Lester (Conf. Computing Frontiers, 2010)

Efficient parallel implementation of multilayer backpropagation networks on SpiNNaker. - Xin Jin 003; Mikel Luján; Luis A. Plana; Alexander D. Rast; Stephen R. Welbourne; Steve B. Furber (Conf. Computing Frontiers, 2010)

SpiNNaker: impact of traffic locality, causality and burstiness on the performance of the interconnection network. - Javier Navaridas; Luis A. Plana; José Miguel-Alonso; Mikel Luján; Stephen B. Furber (Conf. Computing Frontiers, 2010)

Scalable event-driven native parallel processing: the SpiNNaker neuromimetic system. - Alexander D. Rast; Xin Jin 003; Francesco Galluppi; Luis A. Plana; Cameron Patterson; Stephen B. Furber (Conf. Computing Frontiers, 2010)

Description-Level Optimisation of Synthesisable Asynchronous Circuits. - Luis A. Tarazona; Doug A. Edwards; Andrew Bardsley; Luis A. Plana (DSD, 2010)

Algorithm for Mapping Multilayer BP Networks onto the SpiNNaker Neuromorphic Hardware. - Xin Jin 003; Mikel Luján; Muhammad Mukaram Khan; Luis A. Plana; Alexander D. Rast; Stephen R. Welbourne; Stephen B. Furber (ISPDC, 2010)

Modeling Spiking Neural Networks on SpiNNaker. - Xin Jin 003; Mikel Luján; Luis A. Plana; Sergio Davies; Steve Temple; Steve B. Furber (Comput. Sci. Eng., 2010)

System-on-Chip Design and Implementation. - Linda E. M. Brackenbury; Luis A. Plana; Jeffrey Pepper (IEEE Trans. Educ., 2010)

Asynchronous Data-Driven Circuit Synthesis. - Sam Taylor; Doug A. Edwards; Luis A. Plana; Luis A. Tarazona (IEEE Trans. Very Large Scale Integr. Syst., 2010)

Event-Driven Simulation of Arbitrary Spiking Neural Networks on SpiNNaker. - Thomas Sharp; Luis A. Plana; Francesco Galluppi; Steve B. Furber (ICONIP (3), 2011)

An event-driven model for the SpiNNaker virtual synaptic channel. - Alexander D. Rast; Francesco Galluppi; Sergio Davies; Luis A. Plana; Thomas Sharp; Steve B. Furber (IJCNN, 2011)

SpiNNaker: Design and Implementation of a GALS Multicore System-on-Chip. - Luis A. Plana; David M. Clark; Simon Davidson; Steve B. Furber; Jim D. Garside; Eustace Painkras; Jeffrey Pepper; Steve Temple; John Bainbridge (ACM J. Emerg. Technol. Comput. Syst., 2011)

Concurrent heterogeneous neural model simulation on real-time neuromimetic hardware. - Alexander D. Rast; Francesco Galluppi; Sergio Davies; Luis A. Plana; Cameron Patterson; Thomas Sharp; David R. Lester; Steve B. Furber (Neural Networks, 2011)

Event-driven configuration of a neural network CMP system over an homogeneous interconnect fabric. - Mukaram M. Khan; Alexander D. Rast; Javier Navaridas; X. Jin; Luis A. Plana; Mikel Luján; Steve Temple; Cameron Patterson; Dominic Richards; John V. Woods; José Miguel-Alonso; Stephen B. Furber (Parallel Comput., 2011)

An Asynchronous Fully Digital Delay Locked Loop for DDR SDRAM Data Recovery. - Jim D. Garside; Stephen B. Furber; Steve Temple; David M. Clark; Luis A. Plana (ASYNC, 2012)

A hierachical configuration system for a massively parallel neural hardware platform. - Francesco Galluppi; Sergio Davies; Alexander D. Rast; Thomas Sharp; Luis A. Plana; Steve B. Furber (Conf. Computing Frontiers, 2012)

SpiNNaker: A multi-core System-on-Chip for massively-parallel neural net simulation. - Eustace Painkras; Luis A. Plana; Jim D. Garside; Steve Temple; Simon Davidson; Jeffrey Pepper; David M. Clark; Cameron Patterson; Steve B. Furber (CICC, 2012)

Analytical Assessment of the Suitability of Multicast Communications for the SpiNNaker Neuromimetic System. - Javier Navaridas; Mikel Luján; Luis A. Plana; José Miguel-Alonso; Stephen B. Furber (HPCC-ICESS, 2012)

Event-driven MLP implementation on neuromimetic hardware. - Alexander D. Rast; Luis A. Plana; Stephen R. Welbourne; Stephen B. Furber (IJCNN, 2012)

Managing Burstiness and Scalability in Event-Driven Models on the SpiNNaker Neuromimetic System. - Alexander D. Rast; Javier Navaridas; Xin Jin 003; Francesco Galluppi; Luis A. Plana; José Miguel-Alonso; Cameron Patterson; Mikel Luján; Steve B. Furber (Int. J. Parallel Program., 2012)

Scalable communications for a million-core neural processing architecture. - Cameron Patterson; Jim D. Garside; Eustace Painkras; Steve Temple; Luis A. Plana; Javier Navaridas; Thomas Sharp; Steve B. Furber (J. Parallel Distributed Comput., 2012)

Live demonstration: Ethernet communication linking two large-scale neuromorphic systems. - Johannes Partzsch; Christian Mayr 001; Bernhard Vogginger; René Schüffny; Alexander D. Rast; Luis A. Plana; Steve B. Furber (ECCTD, 2013)

Real-Time Interface Board for Closed-Loop Robotic Tasks on the SpiNNaker Neural Computing System. - Christian Denk; Francisco Llobet-Blandino; Francesco Galluppi; Luis A. Plana; Steve B. Furber; Jörg Conradt (ICANN, 2013)

A location-independent direct link neuromorphic interface. - Alexander D. Rast; Johannes Partzsch; Christian Mayr 001; Johannes Schemmel; Stefan Hartmann; Luis A. Plana; Steve Temple; David R. Lester; René Schüffny; Steve B. Furber (IJCNN, 2013)

SpiNNaker: A 1-W 18-Core System-on-Chip for Massively-Parallel Neural Network Simulation. - Eustace Painkras; Luis A. Plana; Jim D. Garside; Steve Temple; Francesco Galluppi; Cameron Patterson; David R. Lester; Andrew D. Brown; Steve B. Furber (IEEE J. Solid State Circuits, 2013)

SpiNNaker: Fault tolerance in a power- and area- constrained large-scale neuromimetic architecture. - Javier Navaridas; Steve B. Furber; Jim D. Garside; Xin Jin 003; Mukaram M. Khan; David R. Lester; Mikel Luján; José Miguel-Alonso; Eustace Painkras; Cameron Patterson; Luis A. Plana; Alexander D. Rast; et al. (Parallel Comput., 2013)

Overview of the SpiNNaker System Architecture. - Steve B. Furber; David R. Lester; Luis A. Plana; Jim D. Garside; Eustace Painkras; Steve Temple; Andrew D. Brown (IEEE Trans. Computers, 2013)

On generating multicast routes for SpiNNaker. - Javier Navaridas; Mikel Luján; Luis A. Plana; Steve Temple; Steve B. Furber (Conf. Computing Frontiers, 2014)

Event-based neural computing on an autonomous mobile platform. - Francesco Galluppi; Christian Denk; Matthias C. Meiner; Terrence C. Stewart; Luis A. Plana; Chris Eliasmith; Stephen B. Furber; Jörg Conradt (ICRA, 2014)

The SpiNNaker Project. - Steve B. Furber; Francesco Galluppi; Steve Temple; Luis A. Plana (Proc. IEEE, 2014)

Accelerating Interconnect Analysis Using High-Level HDLs and FPGA, SpiNNaker as a Case Study. - Mohsen Ghasempour; Jonathan Heathcote; Javier Navaridas; Luis A. Plana; Jim D. Garside; Mikel Luján (FCCM, 2015)

ConvNets experiments on SpiNNaker. - Teresa Serrano-Gotarredona; Bernabé Linares-Barranco; Francesco Galluppi; Luis A. Plana; Stephen B. Furber (ISCAS, 2015)

Analysis of FPGA and software approaches to simulate unconventional computer architectures. - Mohsen Ghasempour; Jonathan Heathcote; Javier Navaridas; Luis A. Plana; Jim D. Garside; Mikel Luján (ReConFig, 2015)

SpiNNaker: Enhanced multicast routing. - Javier Navaridas; Mikel Luján; Luis A. Plana; Steve Temple; Steve B. Furber (Parallel Comput., 2015)

SpiNNaker - Programming Model. - Andrew D. Brown; Stephen B. Furber; Jeffrey S. Reeve; Jim D. Garside; Kier J. Dugan; Luis A. Plana; Steve Temple (IEEE Trans. Computers, 2015)

High performance computing on SpiNNaker neuromorphic platform: A case study for energy efficient image processing. - Indar Sugiarto; Gengting Liu; Simon Davidson; Luis A. Plana; Steve B. Furber (IPCCC, 2016)

Fast Predictive Handshaking in Synchronous FPGAs for Fully Asynchronous Multisymbol Chip Links: Application to SpiNNaker 2-of-7 Links. - Amirreza Yousefzadeh; Luis A. Plana; Steve Temple; Teresa Serrano-Gotarredona; Steve B. Furber; Bernabé Linares-Barranco (IEEE Trans. Circuits Syst. II Express Briefs, 2016)

Parallel distribution of an inner hair cell and auditory nerve model for real-time application. - Robert James; Jim D. Garside; Michael Hopkins; Luis A. Plana; Steve Temple; Simon Davidson; Steve B. Furber (BioCAS, 2017)

Asynchronous interface FIFO design on FPGA for high-throughput NRZ synchronisation. - Gengting Liu; Jim D. Garside; Steve B. Furber; Luis A. Plana; Dirk Koch (FPL, 2017)

Live demonstration: Dynamic voltage and frequency scaling for neuromorphic many-core systems. - Sebastian Höppner; Yexin Yan; Bernhard Vogginger; Andreas Dixius; Johannes Partzsch; Prateek Joshi; Felix Neumärker; Stephan Hartmann 002; Stefan Schiefer; Stefan Scholze; Georg Ellguth; Love Cederstroem; et al. (ISCAS, 2017)

Dynamic voltage and frequency scaling for neuromorphic many-core systems. - Sebastian Höppner; Yexin Yan; Bernhard Vogginger; Andreas Dixius; Johannes Partzsch; Felix Neumärker; Stephan Hartmann 002; Stefan Schiefer; Stefan Scholze; Georg Ellguth; Love Cederstroem; Matthias Eberlein; et al. (ISCAS, 2017)

Live demonstration: Multiplexing AER asynchronous channels over LVDS links with flow-control and clock-correction for scalable neuromorphic systems. - Amirreza Yousefzadeh; Miroslaw Jablonski; Taras Iakymchuk; Alejandro Linares-Barranco; Alfredo Rosado Muñoz; Luis A. Plana; Teresa Serrano-Gotarredona; Steve B. Furber; Bernabé Linares-Barranco (ISCAS, 2017)

Multiplexing AER asynchronous channels over LVDS links with flow-control and clock-correction for scalable neuromorphic systems. - Amirreza Yousefzadeh; Miroslaw Jablonski; Taras Iakymchuk; Alejandro Linares-Barranco; Alfredo Rosado Muñoz; Luis A. Plana; Teresa Serrano-Gotarredona; Stephen B. Furber; Bernabé Linares-Barranco (ISCAS, 2017)

On Multiple AER Handshaking Channels Over High-Speed Bit-Serial Bidirectional LVDS Links With Flow-Control and Clock-Correction on Commercial FPGAs for Scalable Neuromorphic Systems. - Amirreza Yousefzadeh; Miroslaw Jablonski; Taras Iakymchuk; Alejandro Linares-Barranco; Alfredo Rosado; Luis A. Plana; Steve Temple; Teresa Serrano-Gotarredona; Steve B. Furber; Bernabé Linares-Barranco (IEEE Trans. Biomed. Circuits Syst., 2017)

Network-on-chip evaluation for a novel neural architecture. - Markos Kynigos; Javier Navaridas; Luis A. Plana; Steve B. Furber (CF, 2018)

Performance Comparison of Time-Step-Driven versus Event-Driven Neural State Update Approaches in SpiNNaker. - Amirreza Yousefzadeh; Mikel Soto; Teresa Serrano-Gotarredona; Francesco Galluppi; Luis A. Plana; Steve B. Furber; Bernabé Linares-Barranco (ISCAS, 2018)

SpiNNTools: The Execution Engine for the SpiNNaker Platform. - Andrew G. D. Rowley; Christian Y. A. Brenninkmeijer; Simon Davidson; Donal Fellows; Andrew Gait; David R. Lester; Luis A. Plana; Oliver Rhodes; Alan B. Stokes; Steve B. Furber (CoRR, 2018)

Parallel Distribution of an Inner Hair Cell and Auditory Nerve Model for Real-Time Application. - Robert James; Jim D. Garside; Luis A. Plana; Andrew Rowley; Steve B. Furber (IEEE Trans. Biomed. Circuits Syst., 2018)

Real-Time Cortical Simulation on Neuromorphic Hardware. - Oliver Rhodes; Luca Peres; Andrew G. D. Rowley; Andrew Gait; Luis A. Plana; Christian Y. A. Brenninkmeijer; Steve B. Furber (CoRR, 2019)

Dynamic Power Management for Neuromorphic Many-Core Systems. - Sebastian Höppner; Bernhard Vogginger; Yexin Yan; Andreas Dixius; Stefan Scholze; Johannes Partzsch; Felix Neumärker; Stephan Hartmann 002; Stefan Schiefer; Georg Ellguth; Love Cederstroem; Luis A. Plana; et al. (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

spiNNlink: FPGA-Based Interconnect for the Million-Core SpiNNaker System. - Luis A. Plana; Jim D. Garside; Jonathan Heathcote; Jeffrey Pepper; Steve Temple; Simon Davidson; Mikel Luján; Steve B. Furber (IEEE Access, 2020)

Analysis of software and hardware-accelerated approaches to the simulation of unconventional interconnection networks. - Mohsen Ghasempour; Jonathan Heathcote; Javier Navaridas; Luis A. Plana; Jim D. Garside; Mikel Luján (Simul. Model. Pract. Theory, 2020)

A High-Throughput Low-Latency Interface Board for SpiNNaker-in-the-loop Real-Time Systems. - Juan Pablo Romero Bermudez; Luis A. Plana; Andrew Rowley; Mikael Hessel; Jens Egholm Pedersen; Steve B. Furber; Jörg Conradt (ICONS, 2023)

Optimizations for Very Long and Sparse Vector Operations on a RISC-V VPU: A Work-in-Progress. - Gopinath Mahale; Tejas Limbasiya; Muhammad Asad Aleem; Luis A. Plana; Aleksandar Duricic; Alireza Monemi; Xabier Abancens; Teresa Cervero; John D. Davis (ISC Workshops, 2023)