A Comparison of Dual Modular Redundancy and Concurrent Error Detection in Finite Impulse Response Filters Implemented in SRAM-Based FPGAs Through Fault Injection. - Luis Alberto Aranda; Pedro Reviriego; Juan Antonio Maestro (IEEE Trans. Circuits Syst. II Express Briefs, 2018)

ACME: A Tool to Improve Configuration Memory Fault Injection in SRAM-Based FPGAs. - Luis Alberto Aranda; Alfonso Sánchez-Macián; Juan Antonio Maestro (IEEE Access, 2019)

Protection Scheme for Star Tracker Images. - Luis Alberto Aranda; Pedro Reviriego; Ricardo Gonzalez-Toral; Juan Antonio Maestro (IEEE Trans. Aerosp. Electron. Syst., 2019)

Enhancing Instruction TLB Resilience to Soft Errors. - Alfonso Sánchez-Macián; Luis Alberto Aranda; Pedro Reviriego; Vahdaneh Kiani; Juan Antonio Maestro (IEEE Trans. Computers, 2019)

Radiation Hardened Digital Direct Synthesizer With CORDIC for Spaceborne Applications. - Luis Alberto Aranda; Francisco Garcia-Herrero; Luis Esteban; Alfonso Sánchez-Macián; Juan Antonio Maestro (IEEE Access, 2020)

Toward a Fault-Tolerant Star Tracker for Small Satellite Applications. - Luis Alberto Aranda; Pedro Reviriego; Juan Antonio Maestro (IEEE Trans. Aerosp. Electron. Syst., 2020)

An Algorithmic-Based Fault Detection Technique for the 1-D Discrete Cosine Transform. - Luis Alberto Aranda; Alfonso Sánchez-Macián; Juan Antonio Maestro (IEEE Trans. Very Large Scale Integr. Syst., 2020)

Reliability Analysis of ASIC Designs With Xilinx SRAM-Based FPGAs. - Luis Alberto Aranda; Oscar Ruano; Francisco Garcia-Herrero; Juan Antonio Maestro (IEEE Access, 2021)

Fault Injection Emulation for Systems in FPGAs: Tools, Techniques and Methodology, a Tutorial. - Oscar Ruano; Francisco Garcia-Herrero; Luis Alberto Aranda; Alfonso Sánchez-Macián; Laura Rodriguez; Juan Antonio Maestro (Sensors, 2021)

ACME-2: Improving the Extraction of Essential Bits in Xilinx SRAM-Based FPGAs. - Luis Alberto Aranda; Oscar Ruano; Francisco Garcia-Herrero; Juan Antonio Maestro (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

Logic Neural Networks for Efficient FPGA Implementation. - Iván Ramírez; Francisco José García-Espinosa; David Concha; Luis Alberto Aranda (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)