Evaluation of a Reduced Precision Redundancy FFT Design. - Luis Ángel García-Astudillo; Almudena Lindoso; Marta Portela; Luis Entrena (DCIS, 2020)

Reduced Resolution Redundancy: A Novel Approximate Error Mitigation Technique. - Luis Ángel García-Astudillo; Luis Entrena; Almudena Lindoso; Honorio Martín (IEEE Access, 2022)

Formal Verification of Fault-Tolerant Hardware Designs. - Luis Entrena; Antonio J. Sanchez-Clemente; Luis Ángel García-Astudillo; Marta Portela-García; Mario García-Valderas; Almudena Lindoso; Roberto Sarmiento (IEEE Access, 2023)

Error Mitigation Using Optimized Redundancy for Composite Algorithms in FPGAs. - Luis Ángel García-Astudillo; Almudena Lindoso; Luis Entrena (IEEE Trans. Aerosp. Electron. Syst., 2024)