COMPESCE: A Co-design Approach for Memory Subsystem Performance Analysis in HPC Many-Cores. - Antoni Portero; Carlos Falquez; Nam Ho; Polydoros Petrakis; Stepan Nassyr; Manolis Marazakis; Romain Dolbeau; Jorge Alejandro Nocua Cifuentes; Luis Bertran Alvarez; Dirk Pleiter; Estela Suarez (ARCS, 2023)

c2c-gem5: Full System Simulation of Cache-Coherent Chip-to-Chip Interconnects. - Luis Bertran Alvarez; Ghassan Chehaibar; Stephen Busch; Pascal Benoit; David Novo (DATE, 2025)