Sequential logic optimization by redundancy addition and removal. - Luis Entrena; Kwang-Ting Cheng (ICCAD, 1993)

An effective system development environment based on VHDL prototyping. - Serafín Olcoz; Luis Entrena; Luis Berrojo (EURO-DAC, 1995)

VHDL virtual prototyping. - Serafín Olcoz; Luis Entrena; Luis Berrojo (RSP, 1995)

Combinational and sequential logic optimization by redundancy addition and removal. - Luis Entrena-Arrontes; Kwang-Ting Cheng (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995)

Timing optimization by an improved redundancy addition and removal technique. - Luis Entrena; Emilio Olías; Javier Uceda; José Alberto Espejo (EURO-DAC, 1996)

Integrating Symbolic Techniques in ATPG-Based Sequential Logic Optimization. - Enrique San Millán; Luis Entrena; José Alberto Espejo; Silvia Chiusano; Fulvio Corno (DATE, 1999)

Logic Restructuring for MUX-Based FPGAs. - José Alberto Espejo; Luis Entrena; Enrique San Millán; Emilio Olías (EUROMICRO, 1999)

Functional extension of structural logic optimization techniques. - José Alberto Espejo; Luis Entrena; Enrique San Millán; Emilio Olías (ASP-DAC, 2001)

Generalized reasoning scheme for redundancy addition and removal logic optimization. - José Alberto Espejo; Luis Entrena; Enrique San Millán; Emilio Olías (DATE, 2001)

On the Optimization Power of Redundancy Addition and Removal for Sequential Logic Optimization. - Enrique San Millán; Luis Entrena; José Alberto Espejo (DSD, 2001)

On the Optimization Power of Redundancy Addition and Removal Techniques for Sequential Circuits. - Enrique San Millán; Luis Entrena; José Alberto Espejo (ICCAD, 2001)

Automatic Insertion of Fault-Tolerant Structures at the RT Level. - Luis Entrena; Celia López; Emilio Olías (IOLTW, 2001)

Logic Optimization of Unidirectional Circuits with Structural Methods. - Luis Entrena; Celia López; Emilio Olías; Enrique San Millán; José Alberto Espejo (IOLTW, 2001)

New Techniques for Speeding-Up Fault-Injection Campaigns. - Luis Berrojo; Isabel González; Fulvio Corno; Matteo Sonza Reorda; Giovanni Squillero; Luis Entrena; Celia López (DATE, 2002)

Analysis of the Equivalences and Dominances of Transient Faults at the RT Level. - Luis Berrojo; Isabel González; Luis Entrena; Celia López; Fulvio Corno; Matteo Sonza Reorda; Giovanni Squillero (IOLTW, 2002)

An Industrial Environment for High-Level Fault-Tolerant Structures Insertion and Validation. - Luis Berrojo; Isabel González; Fulvio Corno; Matteo Sonza Reorda; Giovanni Squillero; Luis Entrena; Celia López (VTS, 2002)

Data Processing System With Self-reconfigurable Architecture, for Low Cost, Low Power Applications. - Michael G. Lorenz; Luis Mengibar; Luis Entrena; Raul Sánchez-Reillo (FPL, 2003)

State Encoding for Low-Power FSMs in FPGA. - Luis Mengibar; Luis Entrena; Michael G. Lorenz; Raul Sánchez-Reillo (PATMOS, 2003)

Theoretical comparison between sequential redundancy addition and removal and retiming optimization techniques. - Enrique San Millán; Luis Entrena; José Alberto Espejo; Celia López (J. Syst. Archit., 2003)

Architectures for Biometric Match-on-Token Solutions. - Raul Sánchez-Reillo; Judith Liu-Jimenez; Luis Entrena (ECCV Workshop BioAW, 2004)

FPGA Implementation of Biometric Authentication System Based on Hand Geometry. - Celia López-Ongil; Raul Sánchez-Reillo; Judith Liu-Jimenez; Fernando Casado; Leslie Sánchez; Luis Entrena (FPL, 2004)

Power Consumption Reduction Through Dynamic Reconfiguration. - Michael G. Lorenz; Luis Mengibar; Mario García-Valderas; Luis Entrena (FPL, 2004)

Transient Fault Emulation of Hardened Circuits in FPGA Platforms. - Mario García-Valderas; Celia López-Ongil; Marta Portela-García; Luis Entrena (IOLTS, 2004)

Techniques for Fast Transient Fault Grading Based on Autonomous Emulation. - Celia López-Ongil; Mario García-Valderas; Marta Portela-García; Luis Entrena-Arrontes (DATE, 2005)

An Autonomous FPGA-based Emulation System for Fast Fault Tolerant Evaluation. - Celia López-Ongil; Mario García-Valderas; Marta Portela-García; Luis Entrena-Arrontes (FPL, 2005)

Correlation-Based Fingerprint Matching Using FPGAs. - Almudena Lindoso; Luis Entrena; Celia López-Ongil; Judith Liu-Jimenez (FPT, 2005)

Autonomous Transient Fault Emulation on FPGAs for Accelerating Fault Grading. - Celia López-Ongil; Mario García-Valderas; Marta Portela-García; Luis Entrena-Arrontes (IOLTS, 2005)

An Extension of Transient Fault Emulation Techniques to Circuits with Embedded Memories. - Mario García-Valderas; Marta Portela-García; Celia López-Ongil; Luis Entrena-Arrontes (DDECS, 2006)

Fault Injection-based Reliability Evaluation of SoPCs. - Matteo Sonza Reorda; Luca Sterpone; Massimo Violante; Marta Portela-García; Celia López-Ongil; Luis Entrena (ETS, 2006)

Emulation-based Fault Injection in Circuits with Embedded Memories. - Mario García-Valderas; Marta Portela-García; Celia López-Ongil; Luis Entrena (IOLTS, 2006)

Wavelet-Based Fingerprint Region Selection. - Almudena Lindoso; Luis Entrena; Judith Liu-Jimenez (CAIP, 2007)

Correlation-Based Fingerprint Matching with Orientation Field Alignment. - Almudena Lindoso; Luis Entrena; Judith Liu-Jimenez; Enrique San Millán (ICB, 2007)

A Rapid Fault Injection Approach for Measuring SEU Sensitivity in Complex Processors. - Marta Portela-García; Celia López-Ongil; Mario García-Valderas; Luis Entrena (IOLTS, 2007)

High performance FPGA-based image correlation. - Almudena Lindoso; Luis Entrena (J. Real Time Image Process., 2007)

Low power data processing system with self-reconfigurable architecture. - Michael G. Lorenz; Luis Mengibar; Enrique San Millán; Luis Entrena (J. Syst. Archit., 2007)

Logic Transformations by Multiple Wire Network Addition. - Enrique San Millán; Luis Entrena; José Alberto Espejo (DSD, 2008)

Coarse-grain dynamically reconfigurable coprocessor for image processing in SOPC. - Almudena Lindoso; Luis Entrena; Juan Izquierdo; Judith Liu-Jimenez (FPL, 2008)

Smart Hardening for Round-based Encryption Algorithms: Application to Advanced Encryption Standard. - Celia López-Ongil; Alejandro Jiménez-Horas; Marta Portela-García; Mario García-Valderas; Enrique San Millán; Luis Entrena (IOLTS, 2008)

In-depth analysis of digital circuits against soft errors for selective hardening. - Mario García-Valderas; Marta Portela-García; Celia López-Ongil; Luis Entrena (IOLTS, 2009)

Pseudo-random number generation applied to robust modern cryptography: A new technique for block ciphers. - Alejandro Jiménez-Horas; Enrique San Millán; Celia López-Ongil; Marta Portela-García; Mario García-Valderas; Luis Entrena (IOLTS, 2009)

Briefing power/reliability optimization in embedded software design. - Fabian Vargas 001; Claudia A. Rocha; Bernardo Pianta; Marta Portela-García; Celia López-Ongil; Mario García-Valderas; Luis Entrena (IOLTS, 2009)

Study of SEU effects in a Turbo Decoder Bit Error Rate. - Marta Portela-García; Mario García-Valderas; Celia López-Ongil; Luis Entrena; B. Lestriez; Luis Berrojo (LATW, 2009)

SET Emulation Under a Quantized Delay Model. - Mario García-Valderas; Luis Entrena; Raúl Fernández Cardenal; Celia López-Ongil; Marta Portela-García (J. Electron. Test., 2009)

Cryptographically secure pseudo-random bit generator for RFID tags. - Pedro Peris-Lopez; Enrique San Millán; Jan C. A. van der Lubbe; Luis Entrena (ICITST, 2010)

An on-line fault detection technique based on embedded debug features. - Michelangelo Grosso; Matteo Sonza Reorda; Marta Portela-García; Mario García-Valderas; Celia López-Ongil; Luis Entrena (IOLTS, 2010)

Robust cryptographic ciphers with on-line statistical properties validation. - Anna Vaskova; Celia López-Ongil; Alejandro Jiménez-Horas; Enrique San Millán; Luis Entrena (IOLTS, 2010)

AKARI-X: A pseudorandom number generator for secure lightweight systems. - Honorio Martín; Enrique San Millán; Luis Entrena; Julio César Hernández Castro; Pedro Peris-Lopez (IOLTS, 2011)

Evaluation techniques for on-line testing of robust systems based on critical tasks distribution. - Anna Vaskova; Celia López-Ongil; Mario García-Valderas; Marta Portela-García; Luis Entrena (IOLTS, 2011)

Accelerating secure circuit design with hardware implementation of Diehard Battery of tests of randomness. - Anna Vaskova; Celia López-Ongil; Enrique San Millán; Alejandro Jiménez-Horas; Luis Entrena (IOLTS, 2011)

Using an FPGA-based fault injection technique to evaluate software robustness under SEEs: A case study. - Marta Portela-García; Almudena Lindoso; Luis Entrena; Mario García-Valderas; Celia López-Ongil; Bernardo Pianta; Letícia Maria Bolzani Poehls; Fabian Vargas 001 (LATW, 2011)

Fault Injection in Modern Microprocessors Using On-Chip Debugging Infrastructures. - Marta Portela-García; Celia López-Ongil; Mario García-Valderas; Luis Entrena (IEEE Trans. Dependable Secur. Comput., 2011)

SEU sensitivity of robust communication protocols. - Celia López-Ongil; Marta Portela-García; Mario García-Valderas; Anna Vaskova; Luis Entrena; Joaquín Rivas-Abalo; Alberto Martín-Ortega; Javier Martinez-Oter; S. Rodriguez-Bustabad; Ignacio Arruego (IOLTS, 2012)

Logic masking for SET Mitigation Using Approximate Logic Circuits. - Antonio Sanchez-Clemente; Luis Entrena; Mario García-Valderas; Celia López-Ongil (IOLTS, 2012)

Evaluating the Effectiveness of a Software-Based Technique Under SEEs Using FPGA-Based Fault Injection Approach. - Marta Portela-García; Almudena Lindoso; Luis Entrena; Mario García-Valderas; Celia López-Ongil; N. Marroni; Bernardo Pianta; Letícia Maria Bolzani Poehls; Fabian Vargas 001 (J. Electron. Test., 2012)

On the use of embedded debug features for permanent and transient fault resilience in microprocessors. - Marta Portela-García; Michelangelo Grosso; M. Gallardo-Campos; Matteo Sonza Reorda; Luis Entrena; Mario García-Valderas; Celia López-Ongil (Microprocess. Microsystems, 2012)

Soft Error Sensitivity Evaluation of Microprocessors by Multilevel Emulation-Based Fault Injection. - Luis Entrena; Mario García-Valderas; Raúl Fernández Cardenal; Almudena Lindoso; Marta Portela-García; Celia López-Ongil (IEEE Trans. Computers, 2012)

Exploiting the debug interface to support on-line test of control flow errors. - Boyang Du; Matteo Sonza Reorda; Luca Sterpone; Luis Parra; Marta Portela-García; Almudena Lindoso; Luis Entrena (IOLTS, 2013)

Fast fault injection techniques using FPGAs. - Luis Entrena (LATW, 2013)

A new solution to on-line detection of Control Flow Errors. - Boyang Du; Matteo Sonza Reorda; Luca Sterpone; Luis Parra; Marta Portela-García; Almudena Lindoso; Luis Entrena (IOLTS, 2014)

Error masking with approximate logic circuits using dynamic probability estimations. - Antonio Sanchez-Clemente; Luis Entrena; Mario García-Valderas (IOLTS, 2014)

A method to assess the robustness of cryptographic circuits at the design stage. - M. Arévalo-Garbayo; Marta Portela-García; Mario García-Valderas; Celia López-Ongil; Luis Entrena (Microelectron. J., 2014)

Online Test of Control Flow Errors: A New Debug Interface-Based Approach. - Boyang Du; Matteo Sonza Reorda; Luca Sterpone; Luis Parra; Marta Portela-García; Almudena Lindoso; Luis Entrena (IEEE Trans. Computers, 2016)

A Hardware-Software Approach for On-Line Soft Error Mitigation in Interrupt-Driven Applications. - Antonio Martínez-Álvarez; Felipe Restrepo-Calle; Sergio Cuenca-Asensi; Leonardo M. Reyneri; Almudena Lindoso; Luis Entrena (IEEE Trans. Dependable Secur. Comput., 2016)

Error Mitigation Using Approximate Logic Circuits: A Comparison of Probabilistic and Evolutionary Approaches. - Antonio Sanchez-Clemente; Luis Entrena; Radek Hrbacek; Lukás Sekanina (IEEE Trans. Reliab., 2016)

Approximate TMR for selective error mitigation in FPGAs based on testability analysis. - Antonio Sanchez-Clemente; Luis Entrena; Fernanda Lima Kastensmidt (AHS, 2018)

A Novel Use of Approximate Circuits to Thwart Hardware Trojan Insertion and Provide Obfuscation. - Honorio Martín; Luis Entrena; Sophie Dupuis; Giorgio Di Natale (IOLTS, 2018)

On the Entropy of Oscillator-Based True Random Number Generators under Ionizing Radiation. - Honorio Martín; Pedro Martín-Holgado; Pedro Peris-Lopez; Yolanda Morilla; Luis Entrena (Entropy, 2018)

Dynamic control of entropy and power consumption in TRNGs for IoT applications. - Honorio Martín; Enrique San Millán; Luis Entrena-Arrontes (IEICE Electron. Express, 2018)

PTM-based hybrid error-detection architecture for ARM microprocessors. - Manuel Peña-Fernandez; Almudena Lindoso; Luis Entrena; Mario García-Valderas; S. Philippe; Yolanda Morilla; Pedro Martín-Holgado (Microelectron. Reliab., 2018)

Towards a Dependable True Random Number Generator With Self-Repair Capabilities. - Honorio Martín; Giorgio Di Natale; Luis Entrena (IEEE Trans. Circuits Syst. I Regul. Pap., 2018)

Evaluation of a Reduced Precision Redundancy FFT Design. - Luis Ángel García-Astudillo; Almudena Lindoso; Marta Portela; Luis Entrena (DCIS, 2020)

A True Random Number Generator Based on Gait Data for the Internet of You. - Carmen Camara; Honorio Martín; Pedro Peris-Lopez; Luis Entrena (IEEE Access, 2020)

Impact of Atmospheric and Space Radiation on Sensitive Electronic Devices. - Lucas Matana Luza; Frederic Wrobel; Luis Entrena; Luigi Dilillo (ETS, 2022)

Reduced Resolution Redundancy: A Novel Approximate Error Mitigation Technique. - Luis Ángel García-Astudillo; Luis Entrena; Almudena Lindoso; Honorio Martín (IEEE Access, 2022)

Supervised Triple Macrosynchronized Lockstep (STMLS) Architecture for Multicore Processors. - Pablo M. Aviles; Jose A. Belloch; Luis Entrena; Almudena Lindoso (IEEE Access, 2023)

Formal Verification of Fault-Tolerant Hardware Designs. - Luis Entrena; Antonio J. Sanchez-Clemente; Luis Ángel García-Astudillo; Marta Portela-García; Mario García-Valderas; Almudena Lindoso; Roberto Sarmiento (IEEE Access, 2023)

Using Approximate Circuits Against Hardware Trojans. - Honorio Martín; Sophie Dupuis; Giorgio Di Natale; Luis Entrena (IEEE Des. Test, 2023)

Analysing the radiation reliability, performance and energy consumption of low-power SoC through heterogeneous parallelism. - José M. Badía; German Leon; Mario García-Valderas; Jose A. Belloch; Almudena Lindoso; Luis Entrena (Sustain. Comput. Informatics Syst., 2024)

Error Mitigation Using Optimized Redundancy for Composite Algorithms in FPGAs. - Luis Ángel García-Astudillo; Almudena Lindoso; Luis Entrena (IEEE Trans. Aerosp. Electron. Syst., 2024)

Comparative analysis of soft-error sensitivity in LU decomposition algorithms on diverse GPUs. - German Leon; José M. Badía; Jose A. Belloch; Almudena Lindoso; Luis Entrena (J. Supercomput., 2024)