A continuous-time noise-shaping modulator for logarithmic A/D conversion. - Luis Hernández 003; Susana Patón (ISCAS (2), 1999)

A superregenerative receiver for phase and frequency modulated carriers. - Luis Hernández 003; Susana Patón (ISCAS (3), 2002)

A 15 MHz bandwidth sigma-delta ADC with 11 bits of resolution in 0.13μm CMOS. - Antonio Di Giandomenico; Susana Patón; Andreas Wiesbauer; Luis Hernández 003; Thomas Pötscher; Lukas Dörrer (ESSCIRC, 2003)

Continuous time sigma-delta modulators with transmission line resonators and improved jitter and excess loop delay performance. - Luis Hernández 003; Susana Patón (ISCAS (1), 2003)

Linearity enhancement techniques in low OSR, high clock rate multi-bit continuous-time sigma-delta modulators. - Susana Patón; Thomas Pötscher; Antonio Di Giandomenico; Klaus Kolhaupt; Luis Hernández 003; Andreas Wiesbauer; Martin Clara; Ramon Frutos (CICC, 2004)

A jitter insensitive continuous-time ΣΔ modulator using transmission lines. - Luis Hernández 003; Pieter Rombouts; Enrique Prefasi; Susana Patón; Mario Garcia; Celia López (ICECS, 2004)

Modelling and optimization of low pass continuous-time sigma delta modulators for clock jitter noise reduction. - Luis Hernández 003; Andreas Wiesbauer; Susana Patón; Antonio Di Giandomenico (ISCAS (1), 2004)

A 70-mW 300-MHz CMOS continuous-time ΣΔ ADC with 15-MHz bandwidth and 11 bits of resolution. - Susana Patón; Antonio Di Giandomenico; Luis Hernández 003; Andreas Wiesbauer; Thomas Pötscher; Martin Clara (IEEE J. Solid State Circuits, 2004)

Synthesis of sigma delta modulators employing continuous time delays. - Luis Hernández 003; Enrique Prefasi; Susana Patón; Pieter Rombouts (ISCAS (4), 2005)

Analog to digital conversion using a Pulse Width Modulator and an irregular sampling decoder. - Luis Hernández 003; Enrique Prefasi (ICECS, 2006)

Design of Cascaded Continuous-Time Sigma-Delta Modulators. - Susana Patón; Manuel Sanchez-Renedo; Luis Hernández 003; Enrique Prefasi; Andreas Wiesbauer; Antonio Di Giandomenico; David San Segundo (ICECS, 2006)

A 2-2 Discrete Time Cascaded ΣΔ Modulator With NTF Zero Using Interstage Feedback. - Manuel Sanchez-Renedo; Susana Patón; Luis Hernández 003 (ICECS, 2006)

A continuous-time band-pass Sigma Delta modulator implemented in 0.35µm BiCMOS using transmission lines. - Luis Hernández 003; Enrique Prefasi; Pieter Rombouts (ISCAS, 2006)

Spectral shaping of clock jitter errors for continuous time sigma-delta modulators. - Luis Hernández 003; Susana Patón; Andreas Wiesbauer (ISCAS, 2006)

Clock jitter compensation for current steering DACs. - Andreas Wiesbauer; Dietmar Sträußnigg; Richard Gaggl; Martin Clara; Luis Hernández 003; Daniel Gruber (ISCAS, 2006)

A Subsampling Quadrature Σ∆ Modulator Based on Distributed Resonators for Use in Radio Receiver. - Stijn Reekmans; Luis Hernández 003; Enrique Prefasi (IEEE Trans. Circuits Syst. II Express Briefs, 2007)

Resolution enhancement of sigma-delta modulators using a tracking digital filter. - Luis Hernández 003; Susana Patón (ICECS, 2008)

An A/D converter based on pulse width modulation and the walsh-hadamard transform. - Luis Hernández 003; Susana Patón; Enrique Prefasi (ICECS, 2008)

A one-path quadrature bandpass ΣΔ modulator based on distributed resonators at 25 MHz IF. - Enrique Prefasi; Stijn Reekmans; Luis Hernández 003 (ICECS, 2008)

A subsampling bandpass SigmaDelta modulator with lumped and distributed resonators. - Luis Hernández 003; Enrique Prefasi (ISCAS, 2008)

Analog-to-Digital Conversion Using Noise Shaping and Time Encoding. - Luis Hernández 003; Enrique Prefasi (IEEE Trans. Circuits Syst. I Regul. Pap., 2008)

Second-order multi-bit ΣΔ ADC using a Pulse-Width Modulated DAC and an integrating quantizer. - Enrique Prefasi; Ernesto Pun; Luis Hernández 003; Susana Patón (ICECS, 2009)

A 0.1 mm2, Wide Bandwidth Continuous-Time ΔΣ ADC Based on a Time Encoding Quantizer in 0.13 µm CMOS. - Enrique Prefasi; Luis Hernández 003; Susana Patón; Andreas Wiesbauer; Richard Gaggl; Ernesto Pun (IEEE J. Solid State Circuits, 2009)

A 1.2-MHz 10-bit Continuous-Time Sigma-Delta ADC Using a Time Encoding Quantizer. - Luis Hernández 003; Enrique Prefasi; Ernesto Pun; Susana Patón (IEEE Trans. Circuits Syst. II Express Briefs, 2009)

A 0.08 mm2, 7mW Time-Encoding Oversampling Converter with 10 bits and 20MHz BW in 65nm CMOS. - Enrique Prefasi; Susana Patón; Luis Hernández 003; Richard Gaggl; Andreas Wiesbauer; Jörg Hauptmann (ESSCIRC, 2010)

A time encoded decimation filter for noise shaped power DACs. - Luis Hernández 003; Jorge Fernández 001; Enrique Prefasi; Susana Patón (ISCAS, 2010)

Exploiting time resolution in nanometre CMOS data converters. - Luis Hernández 003; Andreas Wiesbauer (ISCAS, 2010)

Continuous Time Cascade Sigma Delta Modulator without digital cancellation filters. - Susana Patón; Juan A. Torreño; Enrique Prefasi; Luis Hernández 003 (ISCAS, 2010)

1.4V 13μW 83dB DR CT-ΣΔ modulator with Dual-Slope quantizer and PWM DAC for biopotential signal acquisition. - Francesco Cannillo; Enrique Prefasi; Luis Hernández 003; Ernesto Pun; Refet Firat Yazicioglu; Chris Van Hoof (ESSCIRC, 2011)

A 7 mW 20 MHz BW Time-Encoding Oversampling Converter Implemented in a 0.08 mm 2 65 nm CMOS Circuit. - Enrique Prefasi; Susana Patón; Luis Hernández 003 (IEEE J. Solid State Circuits, 2011)

Analysis of VCO based noise shaping ADCs linearized by PWM modulation. - Luis Hernández 003; Enrique Prefasi; Susana Patón; Pieter Rombouts (ICECS, 2012)

A distortion corrected passive RC noise shaping ADC for biomedical applications. - Luis Hernández 003; Enrique Prefasi; Susana Patón (ISCAS, 2013)

A multi-stage and time-based continuous time ΣΔ Architecture using a Gated Ring Oscillator. - Juan A. Torreño; Susana Patón; Luis Hernández 003; Enrique Prefasi; M. Presicce; G. Paoli (ISCAS, 2013)

A digitally corrected ADC using a passive pulse frequency modulator. - Eric Gutierrez; Luis Hernández 003; Ulrich Gaier; Sergio Walter; Liang Zou (ICECS, 2014)

A 0.03mm2, 40nm CMOS 1.5GS/s all-digital complementary PWM-GRO. - Enrique Prefasi; Eric Gutierrez; Luis Hernández 003; Susana Patón; Sergio Walter; Ulrich Gaier (ICECS, 2014)

A time-encoding CMOS capacitive sensor readout circuit with flicker noise reduction. - Fernando Cardes; Luis Hernández 003; Javier Escobar; Andreas Wiesbauer; Dietmar Straeussnigg; Richard Gaggl (MWSCAS, 2014)

A low power and low distortion VCO based ADC using a pulse frequency modulator. - Eric Gutierrez; Luis Hernández 003; Ulrich Gaier; Sergio Walter; Liang Zou (MWSCAS, 2014)

A MEMS microphone interface based on a CMOS LC oscillator and a digital sigma-delta modulator. - Fernando Cardes; Ruzica Jevtic; Luis Hernández 003; Andreas Wiesbauer; Dietmar Sträußnigg; Richard Gaggl (ISCAS, 2015)

Spectral analysis of multibit VCO-ADCs and PFM-ADCs with sinusoidal inputs. - Eric Gutierrez; Luis Hernández 003 (ISCAS, 2015)

A noise coupled ΣΔ architecture using a Non Uniform Quantizer. - Juan A. Torreño; Susana Patón; Laura Conesa-Peraleja; Luis Hernández 003; Dietmar Straeussnigg (NORCAS, 2015)

Analytical Evaluation of VCO-ADC Quantization Noise Spectrum Using Pulse Frequency Modulation. - Luis Hernández 003; Eric Gutierrez (IEEE Signal Process. Lett., 2015)

Frequency-encoded integrators applied to filtering and sigma-delta modulation. - Luis Hernández 003; Eric Gutierrez; Fernando Cardes (ISCAS, 2016)

Noise-shaping time-interleaved ADC based on a single ring oscillator and a sampling array. - Andrés Quintero; Carlos Perez; Eric Gutierrez; Luis Hernández 003; Susana Patón (MWSCAS, 2017)

A Highly Linear Ring Oscillator for VCO-based ADCs in 65-nm CMOS. - Leidy Mabel Alvero-Gonzalez; Eric Gutierrez; Luis Hernández 003 (ICECS, 2018)

Optimal NTF zero placement in MASH VCO-ADCs with higher order noise shaping. - Eric Gutierrez; Luis Hernández 003; Susana Patón; Pieter Rombouts (ICECS, 2018)

Why and How VCO-based ADCs can improve instrumentation applications. - Eric Gutierrez; Pieter Rombouts; Luis Hernández 003 (ICECS, 2018)

VCO-ADC Resolution Enhancement Using Maximum Length Sequences. - Luis Hernández 003; Enrique Prefasi; Susana Patón; Eric Gutierrez (ISCAS, 2018)

0.04-mm2 103-dB-A Dynamic Range Second-Order VCO-Based Audio ΣΔ ADC in 0.13-µm CMOS. - Fernando Cardes; Eric Gutierrez; Andrés Quintero; Cesare Buffa; Andreas Wiesbauer; Luis Hernández 003 (IEEE J. Solid State Circuits, 2018)

SNDR Limits of Oscillator-Based Sensor Readout Circuits. - Fernando Cardes; Andrés Quintero; Eric Gutierrez; Cesare Buffa; Andreas Wiesbauer; Luis Hernández 003 (Sensors, 2018)

A Pulse Frequency Modulation Interpretation of VCOs Enabling VCO-ADC Architectures With Extended Noise Shaping. - Eric Gutierrez; Luis Hernández 003; Fernando Cardes; Pieter Rombouts (IEEE Trans. Circuits Syst. I Regul. Pap., 2018)

Resolution Enhancement of VCO-based ADCs by Passive Interpolation and Phase Injection. - Leidy Mabel Alvero-Gonzalez; Luis Hernández 003; Eric Gutierrez (DCIS, 2019)

Continuous Time Sigma-Delta Modulator with VCO-based integrators and optimized NTF zeros. - Victor Medina; Leidy Mabel Alvero-Gonzalez; Eric Gutierrez; Susana Patón; Luis Hernández 003 (ICECS, 2019)

VCO-ADCs with a Quadrature Band-Pass Noise-Transfer-Function. - Eric Gutierrez; Leidy Mabel Alvero-Gonzalez; Luis Hernández 003; Pieter Rombouts (ISCAS, 2019)

VCO-based Feature Extraction Architecture for Low Power Speech Recognition Applications. - Eric Gutierrez; Carlos Perez; Fernando Hernandez; Luis Hernández 003 (MWSCAS, 2019)

A VCO-Based CMOS Readout Circuit for Capacitive MEMS Microphones. - Andrés Quintero; Fernando Cardes; Carlos Perez; Cesare Buffa; Andreas Wiesbauer; Luis Hernández 003 (Sensors, 2019)

Clock Jitter Analysis of Continuous-Time ΣΔ Modulators Based on a Relative Time-Base Projection. - Fernando Cardes; Victor Medina; Susana Patón; Luis Hernández 003 (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

A Pulse Frequency Modulation VCO-ADC in 40 nm. - Eric Gutierrez; Carlos Perez; Luis Hernández 003; Fernando Cardes; Violeta Petrescu; Sergio Walter; Ulrich Gaier (IEEE Trans. Circuits Syst. II Express Briefs, 2019)

VCO-ADC Linearization by Switched Capacitor Frequency-to-Current Conversion. - Rubén Garvi; Leidy Mabel Alvero-Gonzalez; Carlos Perez; Eric Gutierrez; Luis Hernández 003 (ISCAS, 2020)

A Model of Continuous-Time Sigma Delta Modulation Based on Pulse Frequency Encoding. - Victor Medina; Susana Patón; Eric Gutierrez; Luis Hernández 003 (ISCAS, 2020)

Low Power Phase-Encoded MAC Accelerator for Smart Sensors with VCO-based ADCs. - Eric Gutierrez; Carlos Perez; Susana Patón; Luis Hernández 003 (MWSCAS, 2020)

A 73dB-A Audio VCO-ADC Based on a Maximum Length Sequence Generator in 130nm CMOS. - Carlos Perez; Andrés Quintero; Pedro Amaral; Andreas Wiesbauer; Luis Hernández 003 (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

A 55nm CMOS Linearized Oscillator for Audio VCO-ADCs achieving 78dBA of SNDR with $153 mu mathrm{W}$. - Rubén Garvi; Javier Granizo; Angel Salvador; Luis Hernández 003 (ICECS 2022, 2022)

A Phase-Encoded Voice Features Extraction Circuit Using Digital Mixers and Analog Filters based on Ring Oscillators. - Rubén Garvi; Eric Gutierrez; Victor Medina; Luis Hernández 003 (ISCAS, 2022)

A maximally-digital VCO-ADC with inherent mixing input capability. - Victor Medina; Rubén Garvi; Eric Gutierrez; Luis Hernández 003 (ISCAS, 2022)

Optimal reconfiguration instant in ΣΔ Modulators. - Pablo Vera; Dietmar Straeussnigg; Victor Medina; Luis Hernández 003; Susana Patón (ISCAS, 2022)

Validation of a CMOS SNN network based on a time-domain threshold neuron circuit achieving 114.90 pJ/inference on MNIST. - Diego Garcia; Javier Granizo; Luis Hernández 003 (AICAS, 2023)

A CMOS LIF neuron based on a charge-powered oscillator with time-domain threshold logic. - Javier Granizo; Rubén Garvi; Diego Garcia; Luis Hernández 003 (ISCAS, 2023)

Analysis of in-band Spurious Tones of VCO-based Analog Filters and Mitigation Techniques. - Victor Medina; Dante Loi; Pieter Rombouts; Luis Hernández 003 (ISCAS, 2023)

A Different View of Sigma-Delta Modulators Under the Lens of Pulse Frequency Modulation. - Victor Medina; Pieter Rombouts; Luis Hernández 003 (CoRR, 2023)

A Gray-Encoded Ring Oscillator for Efficient Frequency-to-Digital Conversion in VCO-Based ADCs. - Victor Medina; Rubén Garvi; Eric Gutierrez; Susana Patón; Luis Hernández 003 (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

A VCO-ADC Linearized by a Capacitive Frequency-to-Current Converter. - Rubén Garvi; Javier Granizo; Eric Gutierrez; Victor Medina; Andreas Wiesbauer; Luis Hernández 003 (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

A VCO-Based ADC With Inherent Mixing Capability and Local Oscillator Suppression in 55-nm CMOS. - Victor Medina; Rubén Garvi; Eric Gutierrez; Luis Hernández 003 (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

A Scalable and PVT Invariant Spiking Neuron Using Asynchronous CMOS Logic. - Dante Loi; Javier Granizo; Luis Hernández 003 (ISCAS, 2024)

A Second-Order Audio VCO-ADC with 103-dB-A Dynamic Range and Binary-Weighted Internal Architecture. - Victor Medina; Rubén Garvi; Javier Granizo; Pedro Amaral; Luis Hernández 003 (CoRR, 2024)

Analysis of VCO-Based Continuous-Time ΣΔ ADCs Using a Subset of Phases as the Feedback Signal. - Victor Medina; Leidy Mabel Alvero-Gonzalez; Eric Gutierrez; Luis Hernández 003; Susana Patón (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

Analysis of Clock Jitter in VCO-ADCs Under Presence of Mismatch and Blocking Signals. - Javier Granizo; Victor Medina; Luis Hernández 003; Rubén Garvi (ISCAS, 2025)

Explaining Sigma-Delta Modulators with Pulse Frequency Modulation. - Victor Medina; Pieter Rombouts; Luis Hernández 003 (ISCAS, 2025)

A State-Space Model for the Analysis of VCO-Based Filters using PFM. - Simon Ooghe; Luis Hernández 003; Johan Raman; Pieter Rombouts (ISCAS, 2025)