Non-idealities in analog circuits design: What does it really mean? - Luis I. Guerrero-Linares; F. Sandoval-Ibarra; José Raúl Loo-Yau (MWSCAS, 2012)

A simple procedure to synthesize input and output matching networks with short stub for class F-1 PAs. - Alberto Garcia-Osorio; José Raúl Loo-Yau; Pablo Moreno; Luis Ilich Guerrero-Linares; J. Apolinar Reynoso-Hernández (MWSCAS, 2013)

Embedding MATLAB Optimizers in SIMSIDES for the High-Level Design of ΣΔ Modulators. - Beatriz Cortes-Delgadillo; Pablo A. Rodriguez-Navas; Luis I. Guerrero-Linares; José M. de la Rosa 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2018)