Modeling load address behaviour through recurrences. - Luis M. Ramos; Pablo E. Ibáñez 001; Víctor Viñals; José M. Llabería (ISPASS, 2000)

Data prefetching in a cache hierarchy with high bandwidth and capacity. - Luis M. Ramos; José Luis Briz; Pablo E. Ibáñez 001; Víctor Viñals (SIGARCH Comput. Archit. News, 2007)

Low-Cost Adaptive Data Prefetching. - Luis M. Ramos; José Luis Briz; Pablo E. Ibáñez 001; Víctor Viñals (Euro-Par, 2008)

Multi-level Adaptive Prefetching based on Performance Gradient Tracking. - Luis M. Ramos; José Luis Briz; Pablo E. Ibáñez 001; Víctor Viñals (J. Instr. Level Parallelism, 2011)

Exposing Abstraction-Level Interactions with a Parallel Ray Tracer. - Alejandro Valero; Darío Suárez Gracia; Ruben Gran Tejero; Luis M. Ramos; Agustín Navarro-Torres; Adolfo Muñoz 001; Joaquín Ezpeleta; José Luis Briz; Ana C. Murillo; Eduardo Montijano; Javier Resano; María Villarroya-Gaudó; et al. (WCAE@ISCA, 2019)

A learning experience toward the understanding of abstraction-level interactions in parallel applications. - Alejandro Valero; Ruben Gran Tejero; Darío Suárez Gracia; Emanuel A. Georgescu; Joaquín Ezpeleta; Pedro Álvarez 001; Adolfo Muñoz 001; Luis M. Ramos; Pablo Ibáñez 001 (J. Parallel Distributed Comput., 2021)