A special-purpose parallel computer for solving partial differential equations. - Luis Piñuel; Ignacio Martín Llorente; Francisco Tirado (PDP, 1998)

Implementation of Hybrid Context Based Value Predictors Using Value Sequence Classification. - Luis Piñuel; Rafael A. Moreno; Francisco Tirado (Euro-Par, 1999)

Power-Efficient Value Speculation for High-Performance Microprocessors. - Rafael A. Moreno; Luis Piñuel; Silvia Del Pino; Francisco Tirado (EUROMICRO, 2000)

A Power Perspective of Value Speculation for Superscalar Microprocessors. - Rafael A. Moreno; Luis Piñuel; Silvia Del Pino; Francisco Tirado (ICCD, 2000)

Value Prediction as a Cost-Effective Solution to Improve Embedded Processors Performance. - Silvia Del Pino; Luis Piñuel; Rafael A. Moreno; Francisco Tirado (VECPAR, 2000)

Analysing value substitution and confidence estimation for value prediction. - Luis Piñuel; Rafael A. Moreno; Francisco Tirado (J. Syst. Archit., 2001)

-D Wavelet Transform Enhancement on General-Purpose Microprocessors: Memory Hierarchy and SIMD Parallelism Exploitation. - Daniel Chaver; Christian Tenllado; Luis Piñuel; Manuel Prieto 001; Francisco Tirado (HiPC, 2002)

Parallel Wavelet Transform for Large Scale Image Processing. - Daniel Chaver; Manuel Prieto 001; Luis Piñuel; Francisco Tirado (IPDPS, 2002)

Wavelet Transform for Large Scale Image Processing on Modern Microprocessors. - Daniel Chaver; Christian Tenllado; Luis Piñuel; Manuel Prieto 001; Francisco Tirado (VECPAR, 2002)

Analysis of simulation-adapted SPEC 2000 benchmarks. - José Ignacio Gómez; Luis Piñuel; Manuel Prieto 001; Francisco Tirado (SIGARCH Comput. Archit. News, 2002)

SDRAM-Energy-Aware Memory Allocation for Dynamic Multi-Media Applications on Multi-Processor Platforms. - Pol Marchal; José Ignacio Gómez; Davide Bruni; Luca Benini; Luis Piñuel; Francky Catthoor; Henk Corporaal (Embedded Software for SoC, 2003)

SDRAM-Energy-Aware Memory Allocation for Dynamic Multi-Media Applications on Multi-Processor Platforms. - Paul Marchal; José Ignacio Gómez; Luis Piñuel; Davide Bruni; Luca Benini; Francky Catthoor; Henk Corporaal (DATE, 2003)

Vectorization of the 2D Wavelet Lifting Transform Using SIMD Extensions. - Daniel Chaver; Christian Tenllado; Luis Piñuel; Manuel Prieto 001; Francisco Tirado (IPDPS, 2003)

Vectorization of Multigrid Codes Using SIMD ISA Extensions. - Carlos García 001; Roberto Lario; Manuel Prieto 001; Luis Piñuel; Francisco Tirado (IPDPS, 2003)

Branch prediction on demand: an energy-efficient solution. - Daniel Chaver; Luis Piñuel; Manuel Prieto 001; Francisco Tirado; Michael C. Huang 001 (ISLPED, 2003)

Customizing the Branch Predictor to Reduce Complexity and Energy Consumption. - Michael C. Huang 001; Daniel Chaver; Luis Piñuel; Manuel Prieto 001; Francisco Tirado (IEEE Micro, 2003)

Optimizing the Memory Bandwidth with Loop Morphing. - José Ignacio Gómez; Paul Marchal; Sven Verdoolaege; Luis Piñuel; Francky Catthoor (ASAP, 2004)

Exploiting Multilevel Parallelism Within Modern Microprocessors: DWT as a Case Study. - Christian Tenllado; Carlos García 001; Manuel Prieto 001; Luis Piñuel; Francisco Tirado (VECPAR, 2004)

Integrated Task Scheduling and Data Assignment for SDRAMs in Dynamic Applications. - Paul Marchal; Francky Catthoor; Davide Bruni; Luca Benini; José Ignacio Gómez; Luis Piñuel (IEEE Des. Test Comput., 2004)

Improving superword level parallelism support in modern compilers. - Christian Tenllado; Luis Piñuel; Manuel Prieto 001; Francisco Tirado; Francky Catthoor (CODES+ISSS, 2005)

Load-Store Queue Management: an Energy-Efficient Design Based on a State-Filtering Mechanism.. - Fernando Castro; Daniel Chaver; Luis Piñuel; Manuel Prieto 001; Francisco Tirado; Michael C. Huang 001 (ICCD, 2005)

Energy-aware fetch mechanism: trace cache and BTB customization. - Daniel Chaver; Miguel A. Rojas; Luis Piñuel; Manuel Prieto 001; Francisco Tirado; Michael C. Huang 001 (ISLPED, 2005)

JPEG2000 Optimization in General Purpose Microprocessors. - Carlos García 001; Christian Tenllado; Luis Piñuel; Manuel Prieto 001 (PARCO, 2005)

Pack Transposition: Enhancing Superword Level Parallelism Exploitation. - Christian Tenllado; Luis Piñuel; Manuel Prieto 001; Francky Catthoor (PARCO, 2005)

A Power-Efficient and Scalable Load-Store Queue Design. - Fernando Castro; Daniel Chaver; Luis Piñuel; Manuel Prieto 001; Michael C. Huang 001; Francisco Tirado (PATMOS, 2005)

Substituting associative load queue with simple hash tables in out-of-order microprocessors. - Alok Garg; Fernando Castro; Michael C. Huang 001; Daniel Chaver; Luis Piñuel; Manuel Prieto 001 (ISLPED, 2006)

DMDC: Delayed Memory Dependence Checking through Age-Based Filtering. - Fernando Castro; Luis Piñuel; Daniel Chaver; Manuel Prieto 001; Michael C. Huang 001; Francisco Tirado (MICRO, 2006)

A Load-Store Queue Design Based on Predictive State Filtering. - Fernando Castro; Daniel Chaver; Luis Piñuel; Manuel Prieto 001; Michael C. Huang 001; Francisco Tirado (J. Low Power Electron., 2006)

Topic 4: High Performance Architectures and Compilers. - Koen De Bosschere; Ayal Zaks; Michael C. Huang 001; Luis Piñuel (Euro-Par, 2008)

Energy reduction of the fetch mechanism through dynamic adaptation. - Silvia Del Pino; Daniel Chaver; Luis Piñuel; Manuel Prieto 001; Francisco Tirado (IET Comput. Digit. Tech., 2008)

Parallel Implementation of the 2D Discrete Wavelet Transform on Graphics Processing Units: Filter Bank versus Lifting. - Christian Tenllado; Javier Setoain; Manuel Prieto 001; Luis Piñuel; Francisco Tirado (IEEE Trans. Parallel Distributed Syst., 2008)

Stack oriented data cache filtering. - Rodrígo González-Alberquilla; Fernando Castro; Luis Piñuel; Francisco Tirado (CODES+ISSS, 2009)

Using age registers for a simple load-store queue filtering. - Fernando Castro; Daniel Chaver; Luis Piñuel; Manuel Prieto 001; Francisco Tirado (J. Syst. Archit., 2009)

Replacing Associative Load Queues: A Timing-Centric Approach. - Fernando Castro; Regana Noor; Alok Garg; Daniel Chaver; Michael C. Huang 001; Luis Piñuel; Manuel Prieto 001; Francisco Tirado (IEEE Trans. Computers, 2009)

L1 Data Cache Power Reduction Using a Forwarding Predictor. - Pablo Carazo; Rubén Apolloni; Fernando Castro; Daniel Chaver; Luis Piñuel; Francisco Tirado (PATMOS, 2010)

Stack filter: Reducing L1 data cache power consumption. - Rodrígo González-Alberquilla; Fernando Castro; Luis Piñuel; Francisco Tirado (J. Syst. Archit., 2010)

Accelerating Data Race Detection with Minimal Hardware Support. - Rodrígo González-Alberquilla; Karin Strauss; Luis Ceze; Luis Piñuel (Euro-Par (1), 2011)

Hybrid timing-address oriented load-store queue filtering for an x86 architecture. - Rubén Apolloni; Daniel Chaver; Fernando Castro; Luis Piñuel; Manuel Prieto 001; Francisco Tirado (IET Comput. Digit. Tech., 2011)

Reducing Cache Hierarchy Energy Consumption by Predicting Forwarding and Disabling Associative Sets. - Pablo Carazo; Rubén Apolloni; Fernando Castro; Daniel Chaver; Luis Piñuel; Francisco Tirado (J. Circuits Syst. Comput., 2012)

Reducing writes in phase-change memory environments by using efficient cache replacement policies. - Roberto Rodríguez-Rodríguez; Fernando Castro; Daniel Chaver; Luis Piñuel; Francisco Tirado (DATE, 2013)

Data Race Detection with Minimal Hardware Support. - Rekai González-Alberquilla; Fernando Emmanuel Frati; Luis Piñuel; Karin Strauss; Luis Ceze (Comput. J., 2014)

Balancing task- and data-level parallelism to improve performance and energy consumption of matrix computations on the Intel Xeon Phi. - Manuel F. Dolz; Francisco D. Igual; Thomas Ludwig 002; Luis Piñuel; Enrique S. Quintana-Ortí (Comput. Electr. Eng., 2015)

Non-negative Matrix Factorization on Low-Power Architectures and Accelerators: A Comparative Study. - Francisco D. Igual; Carlos García 001; Guillermo Botella; Luis Piñuel; Manuel Prieto-Matías; Francisco Tirado (Comput. Electr. Eng., 2015)

Write-Aware Replacement Policies for PCM-Based Systems. - Roberto Rodríguez-Rodríguez; Fernando Castro; Daniel Chaver; Rekai González-Alberquilla; Luis Piñuel; Francisco Tirado (Comput. J., 2015)

Performance and Energy Optimization of Matrix Multiplication on Asymmetric big.LITTLE Processors. - Sandra Catalán; Francisco D. Igual; Rafael Mayo 002; Luis Piñuel; Enrique S. Quintana-Ortí; Rafael Rodríguez-Sánchez 001 (CoRR, 2015)

A power measurement environment for PCIe accelerators. - Francisco D. Igual; Luis M. Jara; José Ignacio Gómez Pérez; Luis Piñuel; Manuel Prieto-Matías (Comput. Sci. Res. Dev., 2015)

CEPRAM: Compression for Endurance in PCM RAM. - Rodrígo González-Alberquilla; Fernando Castro; Luis Piñuel; Francisco Tirado (J. Circuits Syst. Comput., 2017)

Reuse Detector: Improving the Management of STT-RAM SLLCs. - Roberto Rodríguez-Rodríguez; Javier Díaz; Fernando Castro; Pablo Ibáñez 001; Daniel Chaver; Víctor Viñals; Juan Carlos Saez; Manuel Prieto-Matías; Luis Piñuel; Teresa Monreal Arnal; José María Llabería (Comput. J., 2018)

Short term cloud nowcasting for a solar power plant based on irradiance historical data. - Rafael Caballero; Luis F. Zarzalejo; Álvaro Otero; Luis Piñuel; Stefan Wilbert (J. Comput. Sci. Technol., 2018)

Towards a Malleable Tensorflow Implementation. - Leandro Ariel Libutti; Francisco D. Igual; Luis Piñuel; Laura C. De Giusti; Marcelo R. Naiouf (JCC-BD&ET, 2020)

Spatio-Temporal Resolution of Irradiance Samples in Machine Learning Approaches for Irradiance Forecasting. - Annette Eschenbach; Guillermo Yepes; Christian Tenllado; José Ignacio Gómez Pérez; Luis Piñuel; Luis F. Zarzalejo; Stefan Wilbert (IEEE Access, 2020)

RVfpga: Using a RISC-V Core Targeted to an FPGA in Computer Architecture Education. - Sarah L. Harris; Daniel Chaver; Luis Piñuel; José Ignacio Gómez Pérez; M. Hamza Liaqat; Zubair L. Kakakhel; Olof Kindgren; Robert Owen (FPL, 2021)

Customizing the CVA6 RISC-V Core to Integrate Posit and Quire Instructions. - David Mallasén; Raul Murillo 001; Alberto A. Del Barrio; Guillermo Botella; Luis Piñuel; Manuel Prieto-Matías (DCIS, 2022)

PERCIVAL: Open-Source Posit RISC-V Core With Quire Capability. - David Mallasén; Raul Murillo 001; Alberto A. Del Barrio; Guillermo Botella; Luis Piñuel; Manuel Prieto-Matías (IEEE Trans. Emerg. Top. Comput., 2022)

PERCIVAL: Deploying Posits and Quire Arithmetic into the CVA6 RISC-V Core. - David Mallasén; Raul Murillo 001; Alberto A. Del Barrio; Guillermo Botella; Luis Piñuel; Manuel Prieto-Matías (CF, 2023)

Automatic Generation of Micro-kernels for Performance Portability of Matrix Multiplication on RISC-V Vector Processors. - Francisco D. Igual; Luis Piñuel; Sandra Catalán; Héctor Martínez 002; Adrián Castelló 001; Enrique S. Quintana-Ortí (SC Workshops, 2023)

Improving the Representativeness of Simulation Intervals for the Cache Memory System. - Nicolas Bueno; Fernando Castro; Luis Piñuel; José Ignacio Gómez; Francky Catthoor (IEEE Access, 2024)

Teaching Experiences using the RVfpga Package. - Daniel Chaver; Sarah L. Harris; Luis Piñuel; Olof Kindgren; R. Kravitz; José Ignacio Gómez; Fernando Castro; Katzalin Olcoz; Julio Villalba; A. Grinshpun; F. Gabbay; L. Seed; et al. (CoRR, 2024)

Efficient Low-Latency Multiplication Architecture for NIST Trinomials With RISC-V Integration. - José Luis Imaña; Luis Piñuel; Yao-Ming Kuo; Oscar Ruano; Francisco Garcia-Herrero (IEEE Trans. Circuits Syst. II Express Briefs, 2024)