Gain-boosted Complementary Dynamic Residue Amplifier for a 160 MS/s 61 dB SNDR Noise-Shaping SAR ADC. - Hanie Ghaedrahmati; Jianjun Zhou; Lukang Shi (MWSCAS, 2018)

Single-Loop Delta-Sigma ADC Using Noise-Coupled VCO Quantizer. - Mahmoud Sadollahi; Lukang Shi; Yanchao Wang 001; Gabor C. Temes (MWSCAS, 2018)

A 13b-ENOB Noise Shaping SAR ADC with a Two-Capacitor DAC. - Lukang Shi; Yi Zhang 023; Yanchao Wang 001; Manjunath Kareppagoudr; Mahmoud Sadollahi; Gabor C. Temes (MWSCAS, 2018)

Robust Continuous-Time MASH Delta Sigma Modulator. - Yanchao Wang 001; Lukang Shi; Tao He 001; Yi Zhang 023; Chia-Hung Chen; Gabor C. Temes (MWSCAS, 2018)

Noise-Shaping SAR ADC Using a Two-Capacitor Digitally Calibrated DAC with 85.1 dB DR and 91 dB SFDR. - Lukang Shi; Eashwar Thaigarajan; Rajiv Singh; Erhan Hancioglu; Un-Ku Moon; Gabor C. Temes (MWSCAS, 2020)

A Hybrid Continuous Time Incremental and SAR Two-Step ADC with 90.5dB DR over 1MHz BW. - Yanchao Wang 001; Siladitya Dey 002; Tao He 001; Lukang Shi; Jiawei Zheng; Manjunath Kareppagoudr; Yi Zhang 023; Kazuki Sobue; Koichi Hamashita; Koji Tomioka; Gabor C. Temes (A-SSCC, 2021)

Noise-Shaping SAR ADC Using a Two-Capacitor Digitally Calibrated DAC With 82.6-dB SNDR and 90.9-dB SFDR. - Lukang Shi; Eashwar Thiagarajan; Rajiv Singh; Erhan Hancioglu; Un-Ku Moon; Gabor C. Temes (IEEE Trans. Circuits Syst. I Regul. Pap., 2021)

Multi-Residue Two-Step Incremental ADC. - Faraz Adin; Hanyu Wang; Lukang Shi; Rajiv Singh; Erhan Hancioglu; Gabor C. Temes (MWSCAS, 2024)

98-dB SNDR Multi-Residue Two-Step Incremental ADC With Two-Capacitor SAR. - Faraz Adin; Hanyu Wang; Lukang Shi; Rajiv Singh; Erhan Hancioglu; Gabor C. Temes (IEEE Trans. Circuits Syst. II Express Briefs, 2025)