Low-latency modular packet header parser for FPGA. - Viktor Pus; Lukas Kekely; Jan Korenek (ANCS, 2012)

Fast lookup for dynamic packet filtering in FPGA. - Lukas Kekely; Martin Zádník; Jirí Matousek 002; Jan Korenek (DDECS, 2014)

Design methodology of configurable high performance packet parser for FPGA. - Viktor Pus; Lukas Kekely; Jan Korenek (DDECS, 2014)

CRC based hashing in FPGA using DSP blocks. - Tomás Závodník; Lukas Kekely; Viktor Pus (DDECS, 2014)

Using DSP blocks to compute CRC hash in FPGA (abstract only). - Viktor Pus; Lukas Kekely; Tomás Závodník (FPGA, 2014)

Trade-offs and progressive adoption of FPGA acceleration in network traffic monitoring. - Lukas Kekely; Viktor Pus; Pavel Benácek; Jan Korenek (FPL, 2014)

Software Defined Monitoring of application protocols. - Lukas Kekely; Viktor Pus; Jan Korenek (INFOCOM, 2014)

Hardware accelerated flow measurement of 100 Gb ethernet. - Viktor Pus; Petr Velan; Lukas Kekely; Jan Korenek; Pavel Minarík (IM, 2015)

Software Defined Monitoring of Application Protocols. - Lukas Kekely; Jan Kucera 004; Viktor Pus; Jan Korenek; Athanasios V. Vasilakos (IEEE Trans. Computers, 2016)

Memory Aware Packet Matching Architecture for High-Speed Networks. - Michal Kekely; Lukas Kekely; Jan Korenek (DSD, 2018)

Configurable FPGA Packet Parser for Terabit Networks with Guaranteed Wire-Speed Throughput. - Jakub Cabal; Pavel Benácek; Lukas Kekely; Michal Kekely; Viktor Pus; Jan Korenek (FPGA, 2018)

Accelerated Wire-Speed Packet Capture at 200 Gbps. - Lukas Kekely; Martin Spinler; Stepan Friedl; Jiri Sikora; Jan Korenek (FPL, 2018)

High-Speed Computation of CRC Codes for FPGAs. - Jakub Cabal; Lukás Kekely; Jan Korenek (FPT, 2018)

Demonstration of Full-Duplex Packet Transfers Over PCI Express with Sustained 200 Gbps Throughput. - Lukás Kekely; Martin Spinler; Stepán Friedl; Jiri Sikora; Jan Korenek; Viktor Pus (FPT, 2018)

General IDS Acceleration for High-Speed Networks. - Jan Kucera 004; Lukas Kekely; Adam Piecek; Jan Korenek (ICCD, 2018)

Live demonstration of FPGA based networking accelerator for 200 Gbps data transfers. - Lukas Kekely; Martin Spinler; Stepan Friedl; Jiri Sikora; Jan Korenek (NOMS, 2018)

Effective FPGA Architecture for General CRC. - Lukás Kekely; Jakub Cabal; Jan Korenek (ARCS, 2019)

Multi Buses: Theory and Practical Considerations of Data Bus Width Scaling in FPGAs. - Lukás Kekely; Jakub Cabal; Viktor Pus; Jan Korenek (DSD, 2020)

General memory efficient packet matching FPGA architecture for future high-speed networks. - Michal Kekely; Lukás Kekely; Jan Korenek (Microprocess. Microsystems, 2020)

Increasing Memory Efficiency of Hash-Based Pattern Matching for High-Speed Networks. - Tomás Fukac; Jirí Matousek 002; Jan Korenek; Lukás Kekely (FPT, 2021)