Toward Uniform Approach to Design of Evolvable Hardware Based Systems. - Lukás Sekanina; Azeddien M. Sllame (FPL, 2000)

Relation between Fault Tolerance and Reconfiguration in Cellular Systems. - Lukás Sekanina; Vladimír Drábek (IOLTW, 2000)

Detection of Norwegian Speed Limit Signs. - Lukás Sekanina; Jim Tørresen (ESM, 2002)

Image Filter Design with Evolvable Hardware. - Lukás Sekanina (EvoWorkshops, 2002)

Towards Evolvable IP Cores for FPGAs. - Lukás Sekanina (Evolvable Hardware, 2003)

Easily Testable Image Operators: The Class of Circuits Where Evolution Beats Engineers. - Lukás Sekanina; Richard Ruzicka (Evolvable Hardware, 2003)

From Implementations to a General Concept of Evolvable Machines. - Lukás Sekanina (EuroGP, 2003)

Virtual Reconfigurable Circuits for Real-World Applications of Evolvable Hardware. - Lukás Sekanina (ICES, 2003)

Evolvable components - from theory to hardware implementations. - Lukás Sekanina (Springer, 2004)

Theory and Applications of Evolvable Embedded Systems. - Lukás Sekanina; Vladimír Drábek (ECBS, 2004)

On Routine Implementation of Virtual Evolvable Devices Using COMBO6. - Lukás Sekanina; Stepan Friedl (Evolvable Hardware, 2004)

Evolutionary Design Space Exploration for Median Circuits. - Lukás Sekanina (EvoWorkshops, 2004)

Recognizing Speed Limit Sign Numbers by Evolvable Hardware. - Jim Tørresen; Jorgen W. Bakke; Lukás Sekanina (PPSN, 2004)

Evolving Constructors for Infinitely Growing Sorting Networks and Medians. - Lukás Sekanina (SOFSEM, 2004)

An Evolvable Combinational Unit for FPGAs. - Lukás Sekanina; Stepan Friedl (Comput. Artif. Intell., 2004)

Automatic Discovery of RTL Benchmark Circuits with Predefined Testability Properties. - Tomas Pecenka; Zdenek Kotásek; Lukás Sekanina; Josef Strnadel (Evolvable Hardware, 2005)

Evolutionary Discovering of the Concept of the Discrete State at the Transistor Level. - Lukás Sekanina; Ricardo Salem Zebulum (Evolvable Hardware, 2005)

Evolutionary Design of Gate-Level Polymorphic Digital Circuits. - Lukás Sekanina (EvoWorkshops, 2005)

Providing information from the environment for growing electronic circuits through polymorphic gates. - Michal Bidlo; Lukás Sekanina (GECCO Workshops, 2005)

Intrinsic Evolution of Sorting Networks: A Novel Complete Hardware Implementation for FPGAs. - Jan Korenek; Lukás Sekanina (ICES, 2005)

An Evolvable Image Filter: Experimental Evaluation of a Complete Hardware Implementation in FPGA. - Tomás Martínek; Lukás Sekanina (ICES, 2005)

Intrinsic Evolution of Controllable Oscillators in FPTA-2. - Lukás Sekanina; Ricardo Salem Zebulum (ICES, 2005)

Evolvable Hardware System at Extreme Low Temperatures. - Ricardo Salem Zebulum; Adrian Stoica; Didier Keymeulen; Lukás Sekanina; Rajeshuni Ramesham; Xin Guo 002 (ICES, 2005)

Evolvable Components-From Theory to Hardware Implementations. - Lukás Sekanina; Tughrul Arslan (Genet. Program. Evolvable Mach., 2005)

Evolutionary Design of Arbitrarily Large Sorting Networks Using Development. - Lukás Sekanina; Michal Bidlo (Genet. Program. Evolvable Mach., 2005)

Characterization and Synthesis of Circuits at Extreme Low Temperatures. - Ricardo Salem Zebulum; Didier Keymeulen; Rajeshuni Ramesham; Lukás Sekanina; James Mao; Nikhil Kumar; Adrian Stoica (Evolvable Hardware, 2006)

Evolutionary Design of Digital Circuits: Where Are Current Limits? - Lukás Sekanina (AHS, 2006)

Evolution of Multifunctional Combinational Modules Controlled by the Power Supply Voltage. - Lukás Sekanina; Lukás Starecek; Zbysek Gajda; Zdenek Kotásek (AHS, 2006)

Extrinsic and Intrinsic Evolution of Multifunctional Combinational Modules. - Lukás Sekanina; Tomás Martínek; Zbysek Gajda (IEEE Congress on Evolutionary Computation, 2006)

On dependability of FPGA-based evolvable hardware systems that utilize virtual reconfigurable circuits. - Lukás Sekanina (Conf. Computing Frontiers, 2006)

FITTest_BENCH06: A New Set of Benchmark Circuits Reflecting Diagnostic Properties. - Tomas Pecenka; Zdenek Kotásek; Lukás Sekanina (DDECS, 2006)

Novel Logic Circuits Controlled by Vdd: Transistor-Level Simulations of Polymorphic Combinational Modules. - Lukás Sekanina; Lukás Starecek; Zdenek Kotásek (DDECS, 2006)

Testability Estimation Based on Controllability and Observability Parameters. - Tomas Pecenka; Josef Strnadel; Zdenek Kotásek; Lukás Sekanina (DSD, 2006)

On the Practical Limits of the Evolutionary Digital Filter Design at the Gate Level. - Lukás Sekanina; Zdenek Vasícek (EvoWorkshops, 2006)

Evolutionary circuit design in REPOMO - reconfigurable polymorphic module. - Richard Ruzicka; Lukás Sekanina (Computational Intelligence, 2006)

Evaluation of a New Platform For Image Filter Evolution. - Zdenek Vasícek; Lukás Sekanina (AHS, 2007)

On Some Directions in Security-Oriented Research. - Lukás Sekanina; Tomas Hruska; Tomás Vojnar; Dusan Kolár; Jan Cernocký (BLISS, 2007)

Design and Analysis of a New Self-Testing Adder which Utilizes Polymorphic Gates. - Lukás Sekanina (DDECS, 2007)

Fitness Landscape Analysis and Image Filter Evolution Using Functional-Level CGP. - Karel Slaný; Lukás Sekanina (EuroGP, 2007)

An area-efficient alternative to adaptive median filtering in FPGAs. - Zdenek Vasícek; Lukás Sekanina (FPL, 2007)

Reducing the number of transistors in digital circuits using gate-level evolutionary design. - Zbysek Gajda; Lukás Sekanina (GECCO, 2007)

Evolvable hardware. - Lukás Sekanina (GECCO (Companion), 2007)

Evolution of Polymorphic Self-checking Circuits. - Lukás Sekanina (ICES, 2007)

Reducing the Area on a Chip Using a Bank of Evolved Filters. - Zdenek Vasícek; Lukás Sekanina (ICES, 2007)

Evolutionary functional recovery in virtual reconfigurable circuits. - Lukás Sekanina (ACM J. Emerg. Technol. Comput. Syst., 2007)

Evolved Computing Devices and the Implementation Problem. - Lukás Sekanina (Minds Mach., 2007)

Analysis of Reconfiguration Options for a Reconfigurable Polymorphic Circuit. - Zdenek Vasícek; Ladislav Capka; Lukás Sekanina (AHS, 2008)

Reduction of Test Vectors Volume by Means of Gate-Level Reconfiguration. - Lukás Starecek; Lukás Sekanina; Zdenek Kotásek (DDECS, 2008)

Novel Hardware Implementation of Adaptive Median Filters. - Zdenek Vasícek; Lukás Sekanina (DDECS, 2008)

Hardware Accelerators for Cartesian Genetic Programming. - Zdenek Vasícek; Lukás Sekanina (EuroGP, 2008)

Analysis of Reconfigurable Logic Blocks for Evolvable Digital Architectures. - Lukás Sekanina; Petr Mikusek (EvoWorkshops, 2008)

On Evolutionary Synthesis of Linear Transforms in FPGA. - Zdenek Vasícek; Martin Zádník; Lukás Sekanina; Jirí Tobola (ICES, 2008)

Transistor-Level Evolution of Digital Circuits Using a Special Circuit Simulator. - Ludek Zaloudek; Lukás Sekanina (ICES, 2008)

Physical Demonstration of Polymorphic Self-Checking Circuits. - Richard Ruzicka; Lukás Sekanina; Roman Prokop (IOLTS, 2008)

Adaptive and Evolvable Hardware and Systems: The State of the Art and the Prospectus for Future Development. - Mircea Gh. Negoita; Lukás Sekanina; Adrian Stoica (KES (3), 2008)

Polymorphic Gates in Design and Test of Digital Circuits. - Lukás Sekanina; Lukás Starecek; Zdenek Kotásek; Zbysek Gajda (Int. J. Unconv. Comput., 2008)

Evolution of synthetic RTL benchmark circuits with predefined testability. - Tomas Pecenka; Lukás Sekanina; Zdenek Kotásek (ACM Trans. Design Autom. Electr. Syst., 2008)

Polymorphic FIR Filters with Backup Mode Enabling Power Savings. - Lukás Sekanina; Richard Ruzicka; Zbysek Gajda (AHS, 2009)

Evolution of Impulse Bursts Noise Filters. - Zdenek Vasícek; Michal Bidlo; Lukás Sekanina; Jim Tørresen; Kyrre Glette; Marcus Furuholmen (AHS, 2009)

Gate-level optimization of polymorphic circuits using Cartesian Genetic Programming. - Zbysek Gajda; Lukás Sekanina (IEEE Congress on Evolutionary Computation, 2009)

Evolvable Hardware: From Applications to Implications for the Theory of Computation. - Lukás Sekanina (UC, 2009)

REPOMO32 - New reconfigurable polymorphic integrated circuit for adaptive hardware. - Lukás Sekanina; Richard Ruzicka; Zdenek Vasícek; Roman Prokop; Lukás Fujcik (WEAH, 2009)

Evolutionary design of secrecy amplification protocols for wireless sensor networks. - Petr Svenda; Lukás Sekanina; Václav Matyás (WISEC, 2009)

Evolutionary design and optimization of Wavelet Transforms for image compression in embedded systems. - Rubén Salvador; Félix Moreno; Teresa Riesgo; Lukás Sekanina (AHS, 2010)

A method for design of impulse bursts noise filters optimized for FPGA implementations. - Zdenek Vasícek; Lukás Sekanina; Michal Bidlo (DATE, 2010)

On logic synthesis of conventionally hard to synthesize circuits using genetic programming. - Petr Fiser; Jan Schmidt; Zdenek Vasícek; Lukás Sekanina (DDECS, 2010)

Evolutionary circuit design: Tutorial. - Lukás Sekanina (DDECS, 2010)

On analysis of fabricated polymorphic circuits. - Václav Simek; Richard Ruzicka; Lukás Sekanina (DDECS, 2010)

High Level Validation of an Optimization Algorithm for the Implementation of Adaptive Wavelet Transforms in FPGAs. - Rubén Salvador; Félix Moreno; Teresa Riesgo; Lukás Sekanina (DSD, 2010)

When does Cartesian genetic programming minimize the phenotype size implicitly? - Zbysek Gajda; Lukás Sekanina (GECCO, 2010)

An Efficient Selection Strategy for Digital Circuit Evolution. - Zbysek Gajda; Lukás Sekanina (ICES, 2010)

Evolutionary Design of Reconfiguration Strategies to Reduce the Test Application Time. - Jirí Simácek; Lukás Sekanina; Lukás Starecek (ICES, 2010)

A fast Reconfigurable 2D HW core architecture on FPGAs for evolvable Self-Adaptive Systems. - Andrés Otero; Rubén Salvador; Javier Mora 001; Eduardo de la Torre; Teresa Riesgo; Lukás Sekanina (AHS, 2011)

Evolvable 2D computing matrix model for intrinsic evolution in commercial FPGAs with native reconfiguration support. - Rubén Salvador; Andrés Otero; Javier Mora 001; Eduardo de la Torre; Teresa Riesgo; Lukás Sekanina (AHS, 2011)

Evolutionary design of efficient and robust switching image filters. - Zdenek Vasícek; Michal Bidlo; Lukás Sekanina; Kyrre Glette (AHS, 2011)

A global postsynthesis optimization method for combinational circuits. - Zdenek Vasícek; Lukás Sekanina (DATE, 2011)

Behavior of CMOS polymorphic circuits in high temperature environment. - Richard Ruzicka; Václav Simek; Lukás Sekanina (DDECS, 2011)

Evolution of digital circuits. - Lukás Sekanina (GECCO (Companion), 2011)

A scalable cellular automata based microscopic traffic simulation. - Pavol Korcek; Lukás Sekanina; Otto Fucík (Intelligent Vehicles Symposium, 2011)

Evolution of Iterative Formulas Using Cartesian Genetic Programming. - Milos Minarik; Lukás Sekanina (KES (1), 2011)

Fault Tolerance Analysis and Self-Healing Strategy of Autonomous, Evolvable Hardware Systems. - Rubén Salvador; Andrés Otero; Javier Mora 001; Eduardo de la Torre; Lukás Sekanina; Teresa Riesgo (ReConFig, 2011)

Increasing Fault-Tolerance in Cellular Automata-Based Systems. - Ludek Zaloudek; Lukás Sekanina (UC, 2011)

Evolutionary Approach to Improve Wavelet Transforms for Image Compression in Embedded Systems. - Rubén Salvador; Félix Moreno; Teresa Riesgo; Lukás Sekanina (EURASIP J. Adv. Signal Process., 2011)

Formal verification of candidate solutions for post-synthesis evolutionary optimization in evolvable hardware. - Zdenek Vasícek; Lukás Sekanina (Genet. Program. Evolvable Mach., 2011)

Global Control in Polymorphic Cellular Automata. - Lukás Sekanina; Tomas Komenda (J. Cell. Autom., 2011)

On Evolutionary Synthesis of Compact Polymorphic Combinational Circuits. - Zbysek Gajda; Lukás Sekanina (J. Multiple Valued Log. Soft Comput., 2011)

Image Processing and CGP. - Lukás Sekanina; Simon L. Harding; Wolfgang Banzhaf; Taras Kowaliw (Cartesian Genetic Programming, 2011)

CGP Acceleration Using Field-Programmable Gate Arrays. - Lukás Sekanina; Zdenek Vasícek (Cartesian Genetic Programming, 2011)

Evolution of Electronic Circuits. - Lukás Sekanina; James Alfred Walker; Paul Kaufmann; Marco Platzner (Cartesian Genetic Programming, 2011)

Calibration of Traffic Simulation Models Using Vehicle Travel Times. - Pavol Korcek; Lukás Sekanina; Otto Fucík (ACRI, 2012)

Two-step evolution of polymorphic circuits for image multi-filtering. - Lukás Sekanina; Vojtech Salajka; Zdenek Vasícek (IEEE Congress on Evolutionary Computation, 2012)

On area minimization of complex combinational circuits using cartesian genetic programming. - Zdenek Vasícek; Lukás Sekanina (IEEE Congress on Evolutionary Computation, 2012)

Towards new applications of multi-function logic: Image multi-filtering. - Lukás Sekanina; Vojtech Salajka (DATE, 2012)

A SAT-based fitness function for evolutionary optimization of polymorphic circuits. - Lukás Sekanina; Zdenek Vasícek (DATE, 2012)

Coevolution in Cartesian Genetic Programming. - Michaela Sikulová; Lukás Sekanina (EuroGP, 2012)

Evolutionary Design of Message Efficient Secrecy Amplification Protocols. - Tobiás Smolka; Petr Svenda; Lukás Sekanina; Vashek Matyás (EuroGP, 2012)

Implementation techniques for evolvable HW systems: virtual VS. dynamic reconfiguration. - Rubén Salvador; Andrés Otero; Javier Mora 001; Eduardo de la Torre; Teresa Riesgo; Lukás Sekanina (FPL, 2012)

Evolutionary approach to calibration of cellular automaton based traffic simulation models. - Pavol Korcek; Lukás Sekanina; Otto Fucík (ITSC, 2012)

Estimation of missing values in traffic density maps. - Jiri Petrlik; Pavol Korcek; Otto Fucík; Marian Beszédes; Lukás Sekanina (ITSC, 2012)

Acceleration of Evolutionary Image Filter Design Using Coevolution in Cartesian GP. - Michaela Sikulová; Lukás Sekanina (PPSN (1), 2012)

pecial CAI Section Devoted to MEMICS '11: Preface. - Zdenek Kotásek; Lukás Sekanina; Tomás Vojnar; Jan Bouda; Ivana Cerná (Comput. Informatics, 2012)

Accelerating FPGA-based evolution of wavelet transform filters by optimized task scheduling. - Rubén Salvador; Alberto Vidal; Félix Moreno; Teresa Riesgo; Lukás Sekanina (Microprocess. Microsystems, 2012)

Cellular automata-based systems with fault-tolerance. - Ludek Zaloudek; Lukás Sekanina (Nat. Comput., 2012)

Evolvable Hardware. - Lukás Sekanina (Handbook of Natural Computing, 2012)

Image filter evolution on the Xilinx Zynq Platform. - Roland Dobai; Lukás Sekanina (AHS, 2013)

Multiobjective evolution of approximate multiple constant multipliers. - Jiri Petrlik; Lukás Sekanina (DDECS, 2013)

Towards evolvable systems based on the Xilinx Zynq platform. - Roland Dobai; Lukás Sekanina (ICES, 2013)

Concurrent evolution of hardware and software for application-specific microprogrammed systems. - Milos Minarik; Lukás Sekanina (ICES, 2013)

Approximate circuit design by means of evolvable hardware. - Lukás Sekanina; Zdenek Vasícek (ICES, 2013)

Implementing A Unique Chip Id On A Reconfigurable Polymorphic Circuit. - Lukás Sekanina; Richard Ruzicka; Zdenek Vasícek; Václav Simek; Petr Hanácek (Inf. Technol. Control., 2013)

Advanced Approach to Calibration of Traffic Microsimulation Models Using Travel Times. - Pavol Korcek; Lukás Sekanina; Otto Fucík (J. Cell. Autom., 2013)

Evolution of efficient real-time non-linear image filters for FPGAs. - Zdenek Vasícek; Michal Bidlo; Lukás Sekanina (Soft Comput., 2013)

Self-Reconfigurable Evolvable Hardware System for Adaptive Image Processing. - Rubén Salvador; Andrés Otero; Javier Mora 001; Eduardo de la Torre; Teresa Riesgo; Lukás Sekanina (IEEE Trans. Computers, 2013)

Ubiquity symposium: Evolutionary computation and the processes of life: evolutionary computation in physical world. - Lukás Sekanina (Ubiquity, 2013)

On Evolutionary Approximation of Logic Circuits. - Lukás Sekanina; Zdenek Vasícek (Computing with New Resources, 2014)

Cartesian genetic programming as local optimizer of logic networks. - Lukás Sekanina; Ondrej Ptak; Zdenek Vasícek (IEEE Congress on Evolutionary Computation, 2014)

Multiobjective selection of input sensors for travel times forecasting using support vector regression. - Jiri Petrlik; Otto Fucík; Lukás Sekanina (CIVTS, 2014)

Evolutionary design of approximate multipliers under different error metrics. - Zdenek Vasícek; Lukás Sekanina (DDECS, 2014)

Exploring the Search Space of Hardware / Software Embedded Systems by Means of GP. - Milos Minarik; Lukás Sekanina (EuroGP, 2014)

Towards highly optimized cartesian genetic programming: from sequential via SIMD and thread to massive parallel implementation. - Radek Hrbacek; Lukás Sekanina (GECCO, 2014)

Evolutionary digital circuit design with fast candidate solution establishment in field programmable gate arrays. - Roland Dobai; Kyrre Glette; Jim Tørresen; Lukás Sekanina (ICES, 2014)

Towards compositional coevolution in evolutionary circuit design. - Michaela Sikulová; Gergely Komjathy; Lukás Sekanina (ICES, 2014)

How to evolve complex combinational circuits from scratch? - Zdenek Vasícek; Lukás Sekanina (ICES, 2014)

Multiobjective Selection of Input Sensors for SVR Applied to Road Traffic Prediction. - Jiri Petrlik; Otto Fucík; Lukás Sekanina (PPSN, 2014)

Indirectly Encoded Fitness Predictors Coevolved with Cartesian Programs. - Michaela Sikulová; Jiri Hulva; Lukás Sekanina (EuroGP, 2015)

Circuit Approximation Using Single- and Multi-objective Cartesian GP. - Zdenek Vasícek; Lukás Sekanina (EuroGP, 2015)

A Fast FPGA-Based Classification of Application Protocols Optimized Using Cartesian GP. - David Grochol; Lukás Sekanina; Martin Zádník; Jan Korenek (EvoApplications, 2015)

Evolutionary Approximation of Software for Embedded Systems: Median Function. - Vojtech Mrazek; Zdenek Vasícek; Lukás Sekanina (GECCO (Companion), 2015)

Evolutionary Approximation of Complex Digital Circuits. - Zdenek Vasícek; Lukás Sekanina (GECCO (Companion), 2015)

Towards Robust and Accurate Traffic Prediction Using Parallel Multiobjective Genetic Algorithms and Support Vector Regression. - Jiri Petrlik; Lukás Sekanina (ITSC, 2015)

Evolutionary Approach to Approximate Digital Circuits Design. - Zdenek Vasícek; Lukás Sekanina (IEEE Trans. Evol. Comput., 2015)

Low-Level Flexible Architecture with Hybrid Reconfiguration for Evolvable Hardware. - Roland Dobai; Lukás Sekanina (ACM Trans. Reconfigurable Technol. Syst., 2015)

Principles and Applications of Polymorphic Circuits. - Lukás Sekanina (Evolvable Hardware, 2015)

Functional Equivalence Checking for Evolution of Complex Digital Circuits. - Lukás Sekanina; Zdenek Vasícek (Evolvable Hardware, 2015)

Introduction to approximate computing: Embedded tutorial. - Lukás Sekanina (DDECS, 2016)

Evolutionary Approximation of Edge Detection Circuits. - Petr Dvoracek; Lukás Sekanina (EuroGP, 2016)

Search-based synthesis of approximate circuits implemented into FPGAs. - Zdenek Vasícek; Lukás Sekanina (FPL, 2016)

Evolutionary Design of Fast High-quality Hash Functions for Network Applications. - David Grochol; Lukás Sekanina (GECCO, 2016)

Visualisation and Analysis of Genetic Records Produced by Cartesian Genetic Programming. - Lukás Sekanina; Vlastimil Kapusta (GECCO (Companion), 2016)

Design of power-efficient approximate multipliers for approximate artificial neural networks. - Vojtech Mrazek; Syed Shakib Sarwar; Lukás Sekanina; Zdenek Vasícek; Kaushik Roy 001 (ICCAD, 2016)

Adaptive development of hash functions in FPGA-based network routers. - Roland Dobai; Jan Korenek; Lukás Sekanina (SSCI, 2016)

Evolutionary functional approximation of circuits implemented into FPGAs. - Zdenek Vasícek; Vojtech Mrazek; Lukás Sekanina (SSCI, 2016)

Evolving component library for approximate high level synthesis. - Filip Vaverka; Radek Hrbacek; Lukás Sekanina (SSCI, 2016)

Evolutionary circuit design for fast FPGA-based classification of network application protocols. - David Grochol; Lukás Sekanina; Martin Zádník; Jan Korenek; Vlastimil Kosar (Appl. Soft Comput., 2016)

Evolutionary design of complex approximate combinational circuits. - Zdenek Vasícek; Lukás Sekanina (Genet. Program. Evolvable Mach., 2016)

Error Mitigation Using Approximate Logic Circuits: A Comparison of Probabilistic and Evolutionary Approaches. - Antonio Sanchez-Clemente; Luis Entrena; Radek Hrbacek; Lukás Sekanina (IEEE Trans. Reliab., 2016)

Multi-objective evolution of hash functions for high speed networks. - David Grochol; Lukás Sekanina (CEC, 2017)

EvoApproxSb: Library of approximate adders and multipliers for circuit design and benchmarking of approximation methods. - Vojtech Mrazek; Radek Hrbacek; Zdenek Vasícek; Lukás Sekanina (DATE, 2017)

Towards low power approximate DCT architecture for HEVC standard. - Zdenek Vasícek; Vojtech Mrazek; Lukás Sekanina (DATE, 2017)

Modular framework for detection of inter-ictal spikes in iEEG. - Filip Kesner; Lukás Sekanina; Milan Brazdil (EMBC, 2017)

On Evolutionary Approximation of Sigmoid Function for HW/SW Embedded Systems. - Milos Minarik; Lukás Sekanina (EuroGP, 2017)

Evolutionary approximation of gradient orientation module in HOG-based human detection system. - Michal Wiglasz; Lukás Sekanina (GlobalSIP, 2017)

Approximating complex arithmetic circuits with formal error guarantees: 32-bit multipliers accomplished. - Milan Ceska 002; Jirí Matyás; Vojtech Mrazek; Lukás Sekanina; Zdenek Vasícek; Tomás Vojnar (ICCAD, 2017)

Adaptive and Energy-Efficient Architectures for Machine Learning: Challenges, Opportunities, and Research Roadmap. - Muhammad Shafique 001; Rehan Hafiz; Muhammad Usama Javed; Sarmad Abbas; Lukás Sekanina; Zdenek Vasícek; Vojtech Mrazek (ISVLSI, 2017)

Evolutionary design of hash function pairs for network filters. - Roland Dobai; Jan Korenek; Lukás Sekanina (Appl. Soft Comput., 2017)

Fast Reconfigurable Hash Functions for Network Flow Hashing in FPGAs. - David Grochol; Lukás Sekanina (AHS, 2018)

Design of Quality-Configurable Approximate Multipliers Suitable for Dynamic Environment. - Vojtech Mrazek; Zdenek Vasícek; Lukás Sekanina (AHS, 2018)

ADAC: Automated Design of Approximate Circuits. - Milan Ceska 002; Jirí Matyás; Vojtech Mrazek; Lukás Sekanina; Zdenek Vasícek; Tomás Vojnar (CAV (1), 2018)

Multi-objective Evolution of Ultra-Fast General-Purpose Hash Functions. - David Grochol; Lukás Sekanina (EuroGP, 2018)

Evolving boolean functions for fast and efficient randomness testing. - Vojtech Mrazek; Marek Sýs; Zdenek Vasícek; Lukás Sekanina; Vashek Matyas (GECCO, 2018)

Design Space Exploration for Approximate Implementations of Arithmetic Data Path Primitives. - Lukás Sekanina; Vojtech Mrazek; Zdenek Vasícek (ICECS, 2018)

Cooperative Coevolutionary Approximation in HOG-based Human Detection Embedded System. - Michal Wiglasz; Lukás Sekanina (SSCI, 2018)

Special session: How approximate computing impacts verification, test and reliability. - Lukás Sekanina; Zdenek Vasícek; Alberto Bosio; Marcello Traiola; Paolo Rech; Daniel Oliveira 002; Fernando Fernandes 001; Stefano Di Carlo (VTS, 2018)

Scalable Construction of Approximate Multipliers With Formally Guaranteed Worst Case Error. - Vojtech Mrazek; Zdenek Vasícek; Lukás Sekanina; Honglan Jiang; Jie Han 001 (IEEE Trans. Very Large Scale Integr. Syst., 2018)

Automated Search-Based Functional Approximation for Digital Circuits. - Lukás Sekanina; Zdenek Vasícek; Vojtech Mrazek (Approximate Circuits, 2019)

autoAx: An Automatic Design Space Exploration and Circuit Building Methodology utilizing Libraries of Approximate Components. - Vojtech Mrazek; Muhammad Abdullah Hanif; Zdenek Vasícek; Lukás Sekanina; Muhammad Shafique 001 (DAC, 2019)

TypeCNN: CNN Development Framework With Flexible Data Types. - Petr Rek; Lukás Sekanina (DATE, 2019)

Automated Circuit Approximation Method Driven by Data Distribution. - Zdenek Vasícek; Vojtech Mrazek; Lukás Sekanina (DATE, 2019)

Cartesian Genetic Programming as an Optimizer of Programs Evolved with Geometric Semantic Genetic Programming. - Ondrej Koncal; Lukás Sekanina (EuroGP, 2019)

ALWANN: Automatic Layer-Wise Approximation of Deep Neural Network Accelerators without Retraining. - Vojtech Mrazek; Zdenek Vasícek; Lukás Sekanina; Muhammad Abdullah Hanif; Muhammad Shafique 001 (ICCAD, 2019)

International Symposium on Design and Diagnostics of Electronic Circuits and Systems. - Zoran Stamenkovic; Alberto Bosio; György Cserey; Ondrej Novák; Witold A. Pleskacz; Lukás Sekanina; Andreas Steininger; Goran Stojanovic; Viera Stopjaková (ITC, 2019)

Optimizing Convolutional Neural Networks for Embedded Systems by Means of Neuroevolution. - Filip Badan; Lukás Sekanina (TPNC, 2019)

Adaptive Fitness Predictors in Coevolutionary Cartesian Genetic Programming. - Michaela Drahosova; Lukás Sekanina; Michal Wiglasz (Evol. Comput., 2019)

Efficient On-Chip Randomness Testing Utilizing Machine Learning Techniques. - Vojtech Mrazek; Lukás Sekanina; Roland Dobai; Marek Sýs; Petr Svenda (IEEE Trans. Very Large Scale Integr. Syst., 2019)

Using Libraries of Approximate Circuits in Design of Hardware Accelerators of Deep Neural Networks. - Vojtech Mrazek; Lukás Sekanina; Zdenek Vasícek (AICAS, 2020)

Evolutionary Design of Hash Functions for IPv6 Network Flow Hashing. - David Grochol; Lukás Sekanina (CEC, 2020)

Evolving Cryptographic Boolean Functions with Minimal Multiplicative Complexity. - Jakub Husa; Lukás Sekanina (CEC, 2020)

ApproxFPGAs: Embracing ASIC-Based Approximate Arithmetic Components for FPGA-Based Systems. - Bharath Srinivas Prabakaran; Vojtech Mrazek; Zdenek Vasícek; Lukás Sekanina; Muhammad Shafique 001 (DAC, 2020)

TFApprox: Towards a Fast Emulation of DNN Approximate Hardware Accelerators on GPU. - Filip Vaverka; Vojtech Mrazek; Zdenek Vasícek; Lukás Sekanina (DATE, 2020)

Design, Verification, Test and In-Field Implications of Approximate Computing Systems. - Alberto Bosio; Stefano Di Carlo; Patrick Girard 001; Ernesto Sánchez 001; Alessandro Savino; Lukás Sekanina; Marcello Traiola; Zdenek Vasícek; Arnaud Virazel (ETS, 2020)

Adaptive verifiability-driven strategy for evolutionary approximation of arithmetic circuits. - Milan Ceska 002; Jirí Matyás; Vojtech Mrazek; Lukás Sekanina; Zdenek Vasícek; Tomás Vojnar (Appl. Soft Comput., 2020)

Libraries of Approximate Circuits: Automated Design and Application in CNN Accelerators. - Vojtech Mrazek; Lukás Sekanina; Zdenek Vasícek (IEEE J. Emerg. Sel. Topics Circuits Syst., 2020)

Special issue on highlights of genetic programming 2019 events. - Ting Hu 001; Miguel Nicolau; Lukás Sekanina (Genet. Program. Evolvable Mach., 2020)

Improving the Accuracy and Hardware Efficiency of Neural Networks Using Approximate Multipliers. - Mohammad Saeed Ansari; Vojtech Mrazek; Bruce F. Cockburn; Lukás Sekanina; Zdenek Vasícek; Jie Han 001 (IEEE Trans. Very Large Scale Integr. Syst., 2020)

Evolutionary Neural Architecture Search Supporting Approximate Multipliers. - Michal Pinos; Vojtech Mrazek; Lukás Sekanina (EuroGP, 2021)

Neural Architecture Search and Hardware Accelerator Co-Search: A Survey. - Lukás Sekanina (IEEE Access, 2021)

Evolutionary Algorithms in Approximate Computing: A Survey. - Lukás Sekanina (CoRR, 2021)

Editorial: Special issue on Advancing on Approximate Computing: Methodologies, Architectures and Algorithms. - Mario Barbareschi; Alberto Bosio; Lukás Sekanina; Claus Braun (Future Gener. Comput. Syst., 2021)

Evolutionary Design of Reduced Precision Levodopa-Induced Dyskinesia Classifiers. - Martin Hurta; Michaela Drahosova; Lukás Sekanina; Stephen L. Smith 002; Jane E. Alty (EuroGP, 2022)

Evolutionary Approximation in Non-Local Means Image Filters. - Matej Valek; Lukás Sekanina (SMC, 2022)

Evolutionary approximation and neural architecture search. - Michal Pinos; Vojtech Mrazek; Lukás Sekanina (Genet. Program. Evolvable Mach., 2022)

SagTree: Towards efficient mutation in evolutionary circuit approximation. - Milan Ceska 002; Jirí Matyás; Vojtech Mrazek; Lukás Sekanina; Zdenek Vasícek; Tomás Vojnar (Swarm Evol. Comput., 2022)

Utilizing Genetic Programming to Enhance Polygenic Risk Score Calculation. - Martin Hurta; Jana Schwarzerova; Thomas Nägele; Wolfram Weckwerth; Valentine Provazník; Lukás Sekanina (BIBM, 2023)

ADEE-LID: Automated Design of Energy-Efficient Hardware Accelerators for Levodopa-Induced Dyskinesia Classifiers. - Martin Hurta; Vojtech Mrazek; Michaela Drahosova; Lukás Sekanina (DATE, 2023)

MODEE-LID: Multiobjective Design of Energy-Efficient Hardware Accelerators for Levodopa-Induced Dyskinesia Classifiers. - Martin Hurta; Vojtech Mrazek; Michaela Drahosova; Lukás Sekanina (DDECS, 2023)

Prediction of Inference Energy on CNN Accelerators Supporting Approximate Circuits. - Michal Pinos; Vojtech Mrazek; Lukás Sekanina (DDECS, 2023)

GPAM: Genetic Programming with Associative Memory. - Tadeas Juza; Lukás Sekanina (EuroGP, 2023)

Evolution of Editing Scripts From Examples. - Marek Sedlacek; Lukás Sekanina (GECCO Companion, 2023)

Xel-FPGAs: An End-to-End Automated Exploration Framework for Approximate Accelerators in FPGA-Based Systems. - Bharath Srinivas Prabakaran; Vojtech Mrazek; Zdenek Vasícek; Lukás Sekanina; Muhammad Shafique 001 (ICCAD, 2023)

autoXFPGAs: An End-to-End Automated Exploration Framework for Approximate Accelerators in FPGA-Based Systems. - Bharath Srinivas Prabakaran; Vojtech Mrazek; Zdenek Vasícek; Lukás Sekanina; Muhammad Shafique 001 (CoRR, 2023)

GPAM: Genetic Programming with Associative Memory - datasets for symbolic regression. - Tadeas Juza; Lukás Sekanina (Zenodo, 2023)

Acceleration Techniques for Automated Design of Approximate Convolutional Neural Networks. - Michal Pinos; Vojtech Mrazek; Filip Vaverka; Zdenek Vasícek; Lukás Sekanina (IEEE J. Emerg. Sel. Topics Circuits Syst., 2023)

Automated Verifiability-Driven Design of Approximate Circuits: Exploiting Error Analysis. - Zdenek Vasícek; Vojtech Mrazek; Lukás Sekanina (DATE, 2024)

Exploring Quantization and Mapping Synergy in Hardware-Aware Deep Neural Network Accelerators. - Jan Klhufek; Miroslav Safar; Vojtech Mrazek; Zdenek Vasícek; Lukás Sekanina (DDECS, 2024)

Tutorial: Evolutionary Design Methods in Electronic Design Automation. - Lukás Sekanina (ICCD, 2024)

ApproxDARTS: Differentiable Neural Architecture Search with Approximate Multipliers. - Michal Pinos; Lukás Sekanina; Vojtech Mrazek (IJCNN, 2024)

Semantic mutation operator for a fast and efficient design of bent Boolean functions. - Jakub Husa; Lukás Sekanina (Genet. Program. Evolvable Mach., 2024)

Late Breaking Result: FPGA-Based Emulation and Fault Injection for CNN Inference Accelerators. - Filip Masar; Vojtech Mrazek; Lukás Sekanina (DATE, 2025)

Inference Energy Analysis in Context of Hardware-Aware NAS. - Michal Pinos; Jan Klhufek; Vojtech Mrazek; Lukás Sekanina (DDECS, 2025)

Multi-objective Evolutionary Design of Explainable EEG Classifier. - Martin Hurta; Anna Ovesna; Vojtech Mrazek; Lukás Sekanina (EuroGP, 2025)