OpenMP device offloading to FPGA accelerators. - Lukas Sommer; Jens Korinth; Andreas Koch 001 (ASAP, 2017)

Synthesis of interleaved multithreaded accelerators from OpenMP loops. - Lukas Sommer; Julian Oppermann; Jaco A. Hofmann; Andreas Koch 001 (ReConFig, 2017)

Dependence Graph Preprocessing for Faster Exact Modulo Scheduling in High-Level Synthesis. - Julian Oppermann; Melanie Reuter-Oppermann; Lukas Sommer; Oliver Sinnen; Andreas Koch 001 (FPL, 2018)

Automatic Mapping of the Sum-Product Network Inference Problem to FPGA-Based Accelerators. - Lukas Sommer; Julian Oppermann; Alejandro Molina 001; Carsten Binnig; Kristian Kersting; Andreas Koch 001 (ICCD, 2018)

Extending LLVM for Lightweight SPMD Vectorization: Using SIMD and Vector Instructions Easily from Any Language. - Robin Kruppe; Julian Oppermann; Lukas Sommer; Andreas Koch 001 (CGO, 2019)

DAPHNE - An automotive benchmark suite for parallel programming models on embedded heterogeneous platforms: work-in-progress. - Lukas Sommer; Florian Stock; Leonardo Solis-Vasquez; Andreas Koch 001 (EMSOFT Companion, 2019)

SkyCastle: A Resource-Aware Multi-Loop Scheduler for High-Level Synthesis. - Julian Oppermann; Lukas Sommer; Lukas Weber; Melanie Reuter-Oppermann; Andreas Koch 001; Oliver Sinnen (FPT, 2019)

Resource-Efficient Logarithmic Number Scale Arithmetic for SPN Inference on FPGAs. - Lukas Weber; Lukas Sommer; Julian Oppermann; Alejandro Molina 001; Kristian Kersting; Andreas Koch 001 (FPT, 2019)

High-Throughput Multi-Threaded Sum-Product Network Inference in the Reconfigurable Cloud. - Micha Ober; Jaco A. Hofmann; Lukas Sommer; Lukas Weber; Andreas Koch 001 (H2RC@SC, 2019)

SpExSim: assessing kernel suitability for C-based high-level hardware synthesis. - Julian Oppermann; Lukas Sommer; Andreas Koch 001 (J. Supercomput., 2019)

Exact and Practical Modulo Scheduling for High-Level Synthesis. - Julian Oppermann; Melanie Reuter-Oppermann; Lukas Sommer; Andreas Koch 001; Oliver Sinnen (ACM Trans. Reconfigurable Technol. Syst., 2019)

Extending High-Level Synthesis with High-Performance Computing Performance Visualization. - Jens Huthmann; Artur Podobas; Lukas Sommer; Andreas Koch 001; Kentaro Sano (CLUSTER, 2020)

OpenMP Device Offloading for Embedded Heterogeneous Platforms - Work-in-Progress. - Lukas Sommer; Andreas Koch 001 (EMSOFT, 2020)

Comparison of Arithmetic Number Formats for Inference in Sum-Product Networks on FPGAs. - Lukas Sommer; Lukas Weber; Martin Kumm; Andreas Koch 001 (FCCM, 2020)

OpenMP Device Offloading to FPGAs Using the Nymble Infrastructure. - Jens Huthmann; Lukas Sommer; Artur Podobas; Andreas Koch 001; Kentaro Sano (IWOMP, 2020)

Using Parallel Programming Models for Automotive Workloads on Heterogeneous Systems - a Case Study. - Lukas Sommer; Florian Stock; Leonardo Solis-Vasquez; Andreas Koch 001 (PDP, 2020)

Improving Job Launch Rates in the TaPaSCo FPGA Middleware by Hardware/Software-Co-Design. - Carsten Heinz; Jaco A. Hofmann; Lukas Sommer; Andreas Koch 001 (ROSS@SC, 2020)

SPNC: Accelerating Sum-Product Network Inference on CPUs and GPUs. - Lukas Sommer; Michael Halkenhäuser; Cristian Axenie; Andreas Koch 001 (ASAP, 2021)

Optimizing a Hardware Network Stack to Realize an In-Network ML Inference Application. - Marco Hartmann; Lukas Weber; Johannes Wirth 002; Lukas Sommer; Andreas Koch 001 (H2RC@SC, 2021)

A Framework for the Automatic Generation of FPGA-based Near-Data Processing Accelerators in Smart Storage Systems. - Lukas Weber; Lukas Sommer; Leonardo Solis-Vasquez; Tobias Vinçon; Christian Knödler; Arthur Bernhardt; Ilia Petrov 001; Andreas Koch 001 (IPDPS Workshops, 2021)

SPNC: Fast Sum-Product Network Inference. - Lukas Sommer; Cristian Axenie; Andreas Koch 001 (PKDD/ECML Workshops (1), 2021)

Efficient Operator Sharing Modulo Scheduling for Sum-Product Network Inference on FPGAs. - Hanna Kruppe; Lukas Sommer; Lukas Weber; Julian Oppermann; Cristian Axenie; Andreas Koch 001 (SAMOS, 2021)

The TaPaSCo Open-Source Toolflow. - Carsten Heinz; Jaco A. Hofmann; Jens Korinth; Lukas Sommer; Lukas Weber; Andreas Koch 001 (J. Signal Process. Syst., 2021)

Programming Heterogeneous Systems with General and Domain-Specific Frameworks. - Lukas Sommer (2021)

SPNC: An Open-Source MLIR-Based Compiler for Fast Sum-Product Network Inference on CPUs and GPUs. - Lukas Sommer; Cristian Axenie; Andreas Koch 001 (CGO, 2022)

Exploiting High-Bandwidth Memory for FPGA-Acceleration of Inference on Sum-Product Networks. - Lukas Weber; Johannes Wirth 002; Lukas Sommer; Andreas Koch 001 (IPDPS Workshops, 2022)

Technical Talk: A SYCL Extension for User-Driven Online Kernel Fusion. - Victor Perez 001; Lukas Sommer; Victor Lomüller; Kumudha Narasimhan; Mehdi Goli 001 (IWOCL, 2023)

Leveraging MLIR for Better SYCL Compilation (Poster). - Victor Perez 001; Ettore Tiotto; Whitney Tsang; Arnamoy Bhattacharyya; Lukas Sommer; Victor Lomüller; Jefferson Le Quellec; James Brodman (IWOCL, 2023)

User-driven Online Kernel Fusion for SYCL. - Victor Perez 001; Lukas Sommer; Victor Lomüller; Kumudha Narasimhan; Mehdi Goli 001 (ACM Trans. Archit. Code Optim., 2023)

Experiences Building an MLIR-Based SYCL Compiler. - Ettore Tiotto; Victor Perez 001; Whitney Tsang; Lukas Sommer; Julian Oppermann; Victor Lomüller; Mehdi Goli 001; James Brodman (CGO, 2024)

Runtime Instantiation of Kernels for Fast Fourier Transforms Using SYCL Specialization Constants. - Victor Perez 001; Victor Lomüller; Lukas Sommer; Julian Oppermann; Romain Biessy; Tadej Ciglaric; Mehdi Goli 001 (Euro-Par Workshops (1), 2024)

On Demand Specialization of SYCL Kernels with Specialization Constant Length Allocations (SCLA). - Victor Perez 001; Victor Lomüller; Lukas Sommer; Julian Oppermann; Romain Biessy; Tadej Ciglaric; Mehdi Goli 001 (IWOCL, 2024)

Programming Model Extensions for General-Purpose Processing-In-Memory. - Hyesun Hong; Lukas Sommer; Bongjun Kim; Mikhail Kashkarov; Kumudha Narasimhan; Ilya Veselov; Mehdi Goli 001; Jaeyeon Kim; Ruymán Reyes Castro; Hanwoong Jung (ISC, 2024)