Chip-Level Verification for Parasitic Coupling Effects in Deep-Submicron Digital Designs. - Lun Ye; Foong-Charn Chang; Peter Feldmann; Rakesh Chadha; Nagaraj Ns; Frank Cano (DATE, 1999)

A signal integrity-driven buffer insertion technique for post-routing noise and delay optimization. - Kanad Chakraborty; David E. Long; John P. Fishburn; Kishore Singhal; Lun Ye; Christopher Ortiz (CICC, 2002)

Efficient Techniques for Noise Characterization of Sequential Cells and Macros. - Venkat Rao Vallapenani; Ravi Shankar Chevuri; Bingxiong Xu; Lun Ye; Kanad Chakraborty (VLSI Design, 2006)

Design of Field Station System Based on Internet of Things. - Lun Ye; Limei Dong; Zhipeng Zhang; Xiaotao Song (FSDM, 2018)

Risk Analysis and Utility Function-Based Decision-Making Model for Spinning Reserve Allocations. - Lun Ye; Jiangang Yao; Xu Ouyang; Xiangqian Zhu; Shengjie Yang (IEEE Access, 2021)

The Optimal Sizing of Substation Capacity in a Distribution Network, Considering a Dynamic Time-of-Use Pricing Mechanism. - Dajun Xu; Qiang Fu; Lun Ye; Wenyu Lin; Yuzhou Qian; Kebo Zhang; Jiangang Yao (Sensors, 2022)