Partially Reconfigurable Matrix Multiplication for Area and Time Efficiency on FPGAs. - Luo Jianwen; Jong Ching Chuen (DSD, 2004)

Matrix Inversion on Reconfigurable Hardware using Binary-coded z-path CORDIC. - Luo Jianwen; Jong Ching Chuen (APCCAS, 2006)

An Efficient Algorithm for DPA-resistent RSA. - Yi Wang 016; Jussipekka Leiwo; Thambipillai Srikanthan; Luo Jianwen (APCCAS, 2006)