Compiler-Assisted Thread Level Control Speculation. - Hideyuki Miura; Luong Dinh Hung; Chitaka Iwama; Daisuke Tashiro; Niko Demus Barli; Shuichi Sakai; Hidehiko Tanaka (Euro-Par, 2003)

Complexity Analysis of a Cache Controller for Speculative Multithreading Chip Multiprocessors. - Yoshimitsu Yanagawa; Luong Dinh Hung; Chitaka Iwama; Niko Demus Barli; Shuichi Sakai; Hidehiko Tanaka (HiPC, 2003)

Mitigating Soft Errors in Highly Associative Cache with CAM-based Tag. - Luong Dinh Hung; Masahiro Goshima; Shuichi Sakai (ICCD, 2005)

SEVA: A Soft-Error- and Variation-Aware Cache Architecture. - Luong Dinh Hung; Masahiro Goshima; Shuichi Sakai (PRDC, 2006)

Bus Serialization for Reducing Power Consumption. - Naoya Hatta; Niko Demus Barli; Chitaka Iwama; Luong Dinh Hung; Daisuke Tashiro; Shuichi Sakai; Hidehiko Tanaka (Inf. Media Technol., 2006)

Dynamic Estimation of Task Level Parallelism with Operating System Support. - Luong Dinh Hung; Shuichi Sakai (Inf. Media Technol., 2006)

Utilization of SECDED for soft error and variation-induced defect tolerance in caches. - Luong Dinh Hung; Hidetsugu Irie; Masahiro Goshima; Shuichi Sakai (DATE, 2007)