Scalable FPGA-array for high-performance and power-efficient computation based on difference schemes. - Kentaro Sano; Luzhou Wang; Yoshiaki Hatsuda; Satoru Yamamoto (HPRCTA@SC, 2008)

Local-and-global stall mechanism for systolic computational-memory array on extensible multi-FPGA system. - Luzhou Wang; Kentaro Sano; Satoru Yamamoto (FPT, 2010)

Prototype implementation of array-processor extensible over multiple FPGAs for scalable stencil computation. - Kentaro Sano; Luzhou Wang; Satoru Yamamoto (SIGARCH Comput. Archit. News, 2010)

FPGA-Array with Bandwidth-Reduction Mechanism for Scalable and Power-Efficient Numerical Simulations Based on Finite Difference Methods. - Kentaro Sano; Luzhou Wang; Yoshiaki Hatsuda; Takanori Iizuka; Satoru Yamamoto (ACM Trans. Reconfigurable Technol. Syst., 2010)

Domain-Specific Language and Compiler for Stencil Computation on FPGA-Based Systolic Computational-Memory Array. - Luzhou Wang; Kentaro Sano; Satoru Yamamoto (ARC, 2012)