Using high-level synthesis for rapid design of video processing pipes. - Aydin Emre Guzel; Vecdi Emre Levent; Mustafa Tosun; M. Akif Ozkan; Toygar Akgün; Duygu Buyukaydin; Cengiz Erbas; H. Fatih Ugurdag (EWDTS, 2016)

Fast one- and two-pick fixed-priority selection and muxing circuits. - Mustafa Tosun; M. Akif Ozkan; Aydin Emre Guzel; H. Fatih Ugurdag (EWDTS, 2016)

FPGA-based accelerator design from a domain-specific language. - M. Akif Ozkan; Oliver Reiche; Frank Hannig; Jürgen Teich (FPL, 2016)

Hybrid code description for developing fast and resource efficient image processing architectures. - Konrad Häublein; Marc Reichenbach; Oliver Reiche; M. Akif Ozkan; Dietmar Fey; Frank Hannig; Jürgen Teich (SAMOS, 2016)

Hardware design and analysis of efficient loop coarsening and border handling for image processing. - M. Akif Ozkan; Oliver Reiche; Frank Hannig; Jürgen Teich (ASAP, 2017)

Generating FPGA-based image processing accelerators with Hipacc: (Invited paper). - Oliver Reiche; M. Akif Ozkan; Richard Membarth; Jürgen Teich; Frank Hannig (ICCAD, 2017)

Rapid Design of Real-Time Image Fusion on FPGA using HLS and Other Techniques. - Furkan Aydin; H. Fatih Ugurdag; Vecdi Emre Levent; Aydin Emre Guzel; N. Fajar R. Annafianto; M. Akif Ozkan; Toygar Akgün; Cengiz Erbas (AICCSA, 2018)

Loop Parallelization Techniques for FPGA Accelerator Synthesis. - Oliver Reiche; M. Akif Ozkan; Frank Hannig; Jürgen Teich; Moritz Schmid (J. Signal Process. Syst., 2018)

The Best of Both Worlds: Combining CUDA Graph with an Image Processing DSL. - Bo Qiao 004; M. Akif Özkan; Jürgen Teich; Frank Hannig (DAC, 2020)

Efficient parallel reduction on GPUs with Hipacc. - Bo Qiao 004; Oliver Reiche; M. Akif Özkan; Jürgen Teich; Frank Hannig (SCOPES, 2020)

AnyHLS: High-Level Synthesis With Partial Evaluation. - M. Akif Özkan; Arsène Pérard-Gayot; Richard Membarth; Philipp Slusallek; Roland Leißa; Sebastian Hack; Jürgen Teich; Frank Hannig (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

HipaccVX: wedding of OpenVX and DSL-based code generation. - M. Akif Özkan; Burak Ok; Bo Qiao 004; Jürgen Teich; Frank Hannig (J. Real Time Image Process., 2021)

DSP-Packing: Squeezing Low-precision Arithmetic into FPGA DSP Blocks. - Jan Sommer; M. Akif Özkan; Oliver Keszöcze; Jürgen Teich (FPL, 2022)

Efficient Hardware Acceleration of Sparsely Active Convolutional Spiking Neural Networks. - Jan Sommer; M. Akif Özkan; Oliver Keszöcze; Jürgen Teich (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

Declarative Programming Techniques for Hardware Synthesis of Image Processing Applications. - M. Akif Özkan (2024)