Delay-power performance analysis. - S. Cremoux; M. Aline; Nadine Azémard; Daniel Auvergne (ICECS, 1999)

Feasible Delay Bound Definition. - Nadine Azémard; M. Aline; Philippe Maurine; Daniel Auvergne (VLSI-SOC, 2001)

Delay bound determination for timing closure satisfaction. - Nadine Azémard; M. Aline; Daniel Auvergne (ISCAS (5), 2001)

MVL circuit design and characterization at the transistor level using SUS-LOC. - E. Kinvi-Boh; M. Aline; Olivier Sentieys; Edgar "Dan" Olson (ISMVL, 2003)