Speech encoding and encryption in VLSI. - K. Kalyan Chakravarthy; M. B. Srinivas (ASP-DAC, 2003)

Design of a digital CDMA receiver. - I. Vijay Kumar; M. B. Srinivas (ASP-DAC, 2003)

A Novel Reversible TSG Gate and Its Application for Designing Reversible Carry Look-Ahead and Other Adder Architectures. - Himanshu Thapliyal; M. B. Srinivas (Asia-Pacific Computer Systems Architecture Conference, 2005)

Design And Analysis of A VLSI Based High Performance Low Power Parallel Square Architecture. - Himanshu Thapliyal; M. B. Srinivas; Hamid R. Arabnia (AMCS, 2005)

Design for A Fast And Low Power 2's Complement Multiplier. - Himanshu Thapliyal; M. B. Srinivas; Hamid R. Arabnia (CDES, 2005)

Verilog Coding Style for Efficient Synthesis In FPGA. - Himanshu Thapliyal; M. B. Srinivas; Rameshwar Rao 001; Hamid R. Arabnia (CDES, 2005)

VLSI Implementation of O(n*n) Sorting Algorithms And Their Hardware Comparison. - Saurabh Kotiyal; Himanshu Thapliyal; M. B. Srinivas; Hamid R. Arabnia (CSC, 2005)

A Need of Quantum Computing: Reversible Logic Synthesis of Parallel Binary Adder-Subtractor. - Himanshu Thapliyal; M. B. Srinivas; Hamid R. Arabnia (ESA, 2005)

A Reversible Version of 4 x 4 Bit Array Multiplier With Minimum Gates and Garbage Outputs. - Himanshu Thapliyal; M. B. Srinivas; Hamid R. Arabnia (ESA, 2005)

Reversible Logic Synthesis of Half, Full and Parallel Subtractors. - Himanshu Thapliyal; M. B. Srinivas; Hamid R. Arabnia (ESA, 2005)

Faster RSA Encryption/Decryption Architecture Using an Efficient High Speed Overlay Multiplier. - Himanshu Thapliyal; M. B. Srinivas; Hamid R. Arabnia (Security and Management, 2005)

Implementation of A Fast Square In RSA Encryption/Decryption Architecture. - Himanshu Thapliyal; M. B. Srinivas; Hamid R. Arabnia (Security and Management, 2005)

A novel deep submicron low power bus coding technique. - K. S. Sainarayanan; J. V. R. Ravindra; M. B. Srinivas (Circuits, Signals, and Systems, 2005)

A 32-Bit Binary Floating Point Neuro-Chip. - Keerthi Laal Kala; M. B. Srinivas (ICNC (3), 2005)

Local Language Support for Handheld Devices. - Yaswanth Narvaneni; M. B. Srinivas (ITCC (2), 2005)

The New BCD Subtractor and Its Reversible Logic Implementation. - Himanshu Thapliyal; M. B. Srinivas (Asia-Pacific Computer Systems Architecture Conference, 2006)

Low Power Hierarchical Multiplier and Carry Look-Ahead Architecture. - Himanshu Thapliyal; Neela Gopi; K. K. Pavan Kumar; M. B. Srinivas (AICCSA, 2006)

Novel Reversible Multiplier Architecture Using Reversible TSG Gate. - Himanshu Thapliyal; M. B. Srinivas (AICCSA, 2006)

A Generic Architecture for Intelligent System Hardware. - Keerthi Laal Kala; M. B. Srinivas (APCCAS, 2006)

Novel and Efficient 4: 2 and 5: 2 Compressors with Minimum Number of Transistors Designed for Low-Power Operations. - Pallavi Devi Gopineedi; Himanshu Thapliyal; M. B. Srinivas; Hamid R. Arabnia (ESA, 2006)

Minimizing Simultaneous Switching Noise (SSN) using Modified Odd/Even Bus Invert Method. - K. S. Sainarayanan; J. V. R. Ravindra; M. B. Srinivas (DELTA, 2006)

Modified Montgomery Modular Multiplication Using 4: 2 Compressor and CSA Adder. - Himanshu Thapliyal; Anvesh Ramasahayam; Vivek Reddy Kotha; Kunul Gottimukkula; M. B. Srinivas (DELTA, 2006)

An Efficient Reconfigurable Montgomery Multiplier Architecture for GF(n). - Ramachandruni Venkata Kamala; M. Sudhakar; M. B. Srinivas (DSD, 2006)

A novel, coupling driven, low power bus coding technique for minimizing capacitive crosstalk in VLSI interconnects. - K. S. Sainarayanan; J. V. R. Ravindra; M. B. Srinivas (ISCAS, 2006)

High-Throughput Montgomery Modular Multiplication. - Ramachandruni Venkata Kamala; M. B. Srinivas (VLSI-SoC, 2006)

Novel BCD Adders and Their Reversible Logic Implementation for IEEE 754r Format. - Himanshu Thapliyal; Saurabh Kotiyal; M. B. Srinivas (VLSI Design, 2006)

A New Reversible TSG Gate and Its Application For Designing Efficient Adder Circuits - Himanshu Thapliyal; M. B. Srinivas (CoRR, 2006)

An Extension to DNA Based Fredkin Gate Circuits: Design of Reversible Sequential Circuits using Fredkin Gates - Himanshu Thapliyal; M. B. Srinivas (CoRR, 2006)

Novel Reversible TSG Gate and Its Application for Designing Components of Primitive Reversible/Quantum ALU - Himanshu Thapliyal; M. B. Srinivas (CoRR, 2006)

VLSI Implementation of RSA Encryption System Using Ancient Indian Vedic Mathematics - Himanshu Thapliyal; M. B. Srinivas (CoRR, 2006)

Reduced Area Low Power High Throughput BCD Adders for IEEE 754r Format - Himanshu Thapliyal; Hamid R. Arabnia; M. B. Srinivas (CoRR, 2006)

A Statistical Model for Estimating the Effect of Process Variations on Delay and Slew Metrics for VLSI Interconnects. - J. V. R. Ravindra; M. B. Srinivas (DSD, 2007)

Rule Selection in Fuzzy Systems using Heuristics and Branch Prediction. - Keerthi Laal Kala; M. B. Srinivas (FOCI, 2007)

Area Efficient High Speed Architecture of Bruun's FFT for Software Defined Radio. - Shashank Mittal; Md. Zafar Ali Khan; M. B. Srinivas (GLOBECOM, 2007)

Bus-encoding technique to reduce delay, power and simultaneous switching noise (SSN) in RLC interconnects. - Chittarsu Raghunandan; K. S. Sainarayanan; M. B. Srinivas (ACM Great Lakes Symposium on VLSI, 2007)

Novel architectures for efficient (m, n) parallel counters. - Sreehari Veeramachaneni; Lingamneni Avinash; Kirthi M. Krishna; M. B. Srinivas (ACM Great Lakes Symposium on VLSI, 2007)

Area Efficient Bus Encoding Technique for Minimizing Simultaneous Switching Noise (SSN). - Chittarsu Raghunandan; K. S. Sainarayanan; M. B. Srinivas (ISCAS, 2007)

Novel High-Speed Redundant Binary to Binary converter using Prefix Networks. - Sreehari Veeramachaneni; Kirthi M. Krishna; Lingamneni Avinash; Reddy Puppala Sreekanth; M. B. Srinivas (ISCAS, 2007)

Delay and Power Minimization in VLSI Interconnects with Spatio-Temporal Bus-Encoding Scheme. - K. S. Sainarayanan; Chittarsu Raghunandan; M. B. Srinivas (ISVLSI, 2007)

Novel, High-Speed 16-Digit BCD Adders Conforming to IEEE 754r Format. - Sreehari Veeramachaneni; Kirthi M. Krishna; Lingamneni Avinash; Reddy Puppala Sreekanth; M. B. Srinivas (ISVLSI, 2007)

Generating reduced order models using subspace iteration for linear RLC circuits in nanometer designs. - J. V. R. Ravindra; M. B. Srinivas (Nano-Net, 2007)

A Comparative Study of Different FFT Architectures for Software Defined Radio. - Shashank Mittal; Md. Zafar Ali Khan; M. B. Srinivas (SAMOS, 2007)

Modeling and analysis of crosstalk for distributed RLC interconnects using difference model approach. - J. V. R. Ravindra; Srinivas Bala Mandalika (SBCCI, 2007)

A unified and reconfigurable Montgomery Multiplier architecture without four-to-two CSA. - Sudhakar Maddi; M. B. Srinivas (SBCCI, 2007)

Bus encoding schemes for minimizing delay in VLSI interconnects. - K. S. Sainarayanan; Chittarsu Raghunandan; M. B. Srinivas (SBCCI, 2007)

A bit-sliced, scalable and unified montgomery multiplier architecture for RSA and ECC. - M. Sudhakar; Ramachandruni Venkata Kamala; M. B. Srinivas (VLSI-SoC, 2007)

A Unified, Reconfigurable Architecture for Montgomery Multiplication in Finite Fields GF(p) and GF(2^n). - M. Sudhakar; Ramachandruni Venkata Kamala; M. B. Srinivas (VLSI Design, 2007)

Novel Architectures for High-Speed and Low-Power 3-2, 4-2 and 5-2 Compressors. - Sreehari Veeramachaneni; Kirthi M. Krishna; Lingamneni Avinash; Reddy Puppala Sreekanth; M. B. Srinivas (VLSI Design, 2007)

Delay and Energy Efficient Coding Techniques for Capacitive Interconnects. - J. V. R. Ravindra; M. B. Srinivas (J. Circuits Syst. Comput., 2007)

New and Improved Architectures for Montgomery Modular Multiplication. - M. Sudhakar; Ramachandruni Venkata Kamala; M. B. Srinivas (Mob. Networks Appl., 2007)

Generic sub-space algorithm for generating reduced order models of linear time varying vlsi circuits. - J. V. R. Ravindra; M. B. Srinivas (ACM Great Lakes Symposium on VLSI, 2008)

Process Variation Aware Bus-Coding Scheme for Delay Minimization in VLSI Interconnects. - Chittarsu Raghunandan; K. S. Sainarayanan; M. B. Srinivas (ISQED, 2008)

A Novel Encoding Scheme for Delay and Energy Minimization in VLSI Interconnects with Built-In Error Detection. - Lingamneni Avinash; Kirthi Krishna Muntimadugu; M. B. Srinivas (ISVLSI, 2008)

Training Data Compression Algorithms and Reliability in Large Wireless Sensor Networks. - Vasanth Iyer; Rammurthy Garimella; M. B. Srinivas (SUTC, 2008)

A Novel Carry-Look Ahead Approach to a Unified BCD and Binary Adder/Subtractor. - Sreehari Veeramachaneni; Kirthi M. Krishna; Prateek G. V.; Subroto S.; Bharat S.; M. B. Srinivas (VLSI Design, 2008)

Transition Inversion Based Low Power Data Coding Scheme for Synchronous Serial Communication. - Abinesh Ramachandran; Bharghava Rajaram; Mandalika B. Srinivas (ISVLSI, 2009)

All Digital Duty Cycle Correction Circuit in 90nm Based on Mutex. - Swathi Ramasahayam; M. B. Srinivas (ISVLSI, 2009)

A High Performance Unified BCD and Binary Adder/Subtractor. - Anshul Singh; Aman Gupta; Sreehari Veeramachaneni; M. B. Srinivas (ISVLSI, 2009)

Multi-hop scheduling and local data link aggregation dependant Qos in modeling and simulation of power-aware wireless sensor networks. - Vasanth Iyer; S. Sitharama Iyengar; Garimella Rama Murthy; Bertrand Hochet; Vir V. Phoha; M. B. Srinivas (IWCMC, 2009)

A novel low power, variable resolution pipelined ADC. - Mahesh Kumar Adimulam; Sreehari Veeramachaneni; M. B. Srinivas (SoCC, 2009)

Design of a Low Power, Variable-Resolution Flash ADC. - Sreehari Veeramachaneni; Mahesh Kumar Adimulam; Venkat Tummala; M. B. Srinivas (VLSI Design, 2009)

A Novel Low Power, Variable Resolution Flash Analog-to-Digital Converter. - Mahesh Kumar Adimulam; Sreehari Veeramachaneni; M. B. Srinivas (J. Low Power Electron., 2009)

Efficient Reversible Logic Design of BCD Subtractors. - Himanshu Thapliyal; Hamid R. Arabnia; M. B. Srinivas (Trans. Comput. Sci., 2009)

Low power, variable resolution pipelined analog to Digital converter with sub flash architecture. - Mahesh Kumar Adimulam; Krishna Kumar Movva; Sreehari Veeramachaneni; N. Moorthy Muthukrishnan; Mandalika B. Srinivas (APCCAS, 2010)

An efficient ODT calibration scheme for improved signal integrity in memory interface. - Gudipati Kalyan; M. B. Srinivas (APCCAS, 2010)

Implementation of low power FFT structure using a method based on conditionally coded blocks. - Sandeep Saini; Anurag Mahajan; Srinivas B. Mandalika (APCCAS, 2010)

A low power, variable resolution two-step flash ADC. - Mahesh Kumar Adimulam; Krishna Kumar Movva; Sreehari Veeramachaneni; N. Moorthy Muthukrishnan; M. B. Srinivas (ACM Great Lakes Symposium on VLSI, 2010)

A new approach to minimize leakage power in nano-scale VLSI adder. - Pradeep Jamwal; M. B. Srinivas; G. V. K. Sarma; M. Murali Krishna (ICWET, 2010)

Effects of channel SNR in mobile cognitive radios and coexisting deployment of cognitive wireless sensor networks. - Vasanth Iyer; S. Sitharama Iyengar; Garimella Rama Murthy; Nandan Parameswaran; Dhananjay Singh 001; Mandalika B. Srinivas (IPCCC, 2010)

A Novel, Variable Resolution Flash ADC with Sub Flash Architecture. - Mahesh Kumar Adimulam; Sreehari Veeramachaneni; N. Moorthy Muthukrishnan; M. B. Srinivas (ISVLSI, 2010)

An Alternative approach to Buffer Insertion for Delay and Power Reduction in VLSI Interconnects. - Sandeep Saini; Mahesh Kumar Adimulam; Sreehari Veeramachaneni; M. B. Srinivas (VLSI Design, 2010)

An Alternate Approach to Buffer Insertion for Delay and Power Reduction in VLSI Interconnects. - Sandeep Saini; A. Mahesh Kumar; Sreehari Veeramachaneni; M. B. Srinivas (J. Low Power Electron., 2010)

A Unified Architecture for BCD and Binary Adder/Subtractor. - Chetan Kumar V.; P. Sai Phaneendra; Syed Ershad Ahmed; Sreehari Veeramachaneni; N. Moorthy Muthukrishnan; M. B. Srinivas (DSD, 2011)

Increment/decrement/2's complement/priority encoder circuit for varying operand lengths. - P. Sai Phaneendra; Chetan Vudadha; Syed Ershad Ahmed; Sreehari Veeramachaneni; N. Moorthy Muthukrishnan; M. B. Srinivas (ISCIT, 2011)

A Multiple-Bandwidth 10-bit SAR Analog to Digital Converter. - Mahesh Kumar Adimulam; Krishna Kumar Movva; Sreehari Veeramachaneni; N. Moorthy Muthukrishnan; M. B. Srinivas (ISED, 2011)

A Reconfigurable INC/DEC/2's Complement/Priority Encoder Circuit with Improved Decision Block. - Chetan Kumar V.; P. Sai Phaneendra; Syed Ershad Ahmed; Sreehari Veeramachaneni; N. Moorthy Muthukrishnan; M. B. Srinivas (ISED, 2011)

A Prefix Based Reconfigurable Adder. - Chetan Kumar V.; Sai Phaneendra P.; Syed Ershad Ahmed; Sreehari Veeramachaneni; N. Moorthy Muthukrishnan; M. B. Srinivas (ISVLSI, 2011)

On the Suitability of Multi-Core Processing for Embedded Automotive Systems. - Santosh Kumar Jena; M. B. Srinivas (CyberC, 2012)

CNFET based ternary magnitude comparator. - Chetan Vudadha; Phaneendra P. Sai; Sreehari Veeramachaneni; M. B. Srinivas (ISCIT, 2012)

A Modified Twin Precision Multiplier with 2D Bypassing Technique. - Syed Ershad Ahmed; Sibi Abraham; Sreehari Veeramachaneni; N. Moorthy Muthukrishnan; M. B. Srinivas (ISED, 2012)

Design and Analysis of Reversible Ripple, Prefix and Prefix-Ripple Hybrid Adders. - Chetan Vudadha; P. Sai Phaneendra; Syed Ershad Ahmed; Sreehari Veeramachaneni; N. Moorthy Muthukrishnan; Mandalika B. Srinivas (ISVLSI, 2012)

Design of Prefix-Based Optimal Reversible Comparator. - Chetan Vudadha; P. Sai Phaneendra; Sreehari Veeramachaneni; Syed Ershad Ahmed; N. Moorthy Muthukrishnan; Mandalika B. Srinivas (ISVLSI, 2012)

Low-Power Self Reconfigurable Multiplexer Based Decoder for Adaptive Resolution Flash ADCs. - Chetan Vudadha; Goutham Makkena; M. Venkata Swamy Nayudu; P. Sai Phaneendra; Syed Ershad Ahmed; Sreehari Veeramachaneni; N. Moorthy Muthukrishnan; M. B. Srinivas (VLSI Design, 2012)

Uniform approximation of Gaussian wavelet for biomedical signal processing in analog domain. - Goutham Makkena; Prabhakara Rao; M. B. Srinivas (EMBC, 2013)

A smart phone/tablet based mobile health care system for developing countries. - Avinash S. Vaidya; M. B. Srinivas; P. Himabindu; Daria Jumaxanova (EMBC, 2013)

A unified flagged prefix constant addition-subtraction scheme for design of area and power efficient binary floating-point and constant integer arithmetic circuits. - Soumya Ganguly; Abhishek Mittal; Syed Ershad Ahmed; M. B. Srinivas (APCCAS, 2014)

Estimation of Arterial Stiffness through Pulse Transit Time Measurement. - Avinash S. Vaidya; T. S. L. Radhika; M. B. Srinivas; Mannan Mridha (BIODEVICES, 2014)

A New Design of an N-Bit Reversible Arithmetic Logic Unit. - Subhankar Pal; Chetan Vudadha; P. Sai Phaneendra; Sreehari Veeramachaneni; Srinivas B. Mandalika (ISED, 2014)

A reconfigurable 0-L1-L2 S-MASH2 modulator with high-level sizing and power estimation. - Abhilash K. N; M. B. Srinivas (SoCC, 2014)

An Optimized Design of Reversible Quantum Comparator. - P. Sai Phaneendra; Chetan Vudadha; Sreehari Veeramachaneni; M. B. Srinivas (VLSID, 2014)

A Novel Low Power Error Detection Logic for Inexact Leading Zero Anticipator in Floating Point Units. - B. Naveen Kumar Reddy; M. Chandra Sekhar; Sreehari Veeramachaneni; M. B. Srinivas (VLSID, 2014)

A Decimal/Binary Multi-operand Adder Using a Fast Binary to Decimal Converter. - Ch. Santosh Varma; Syed Ershad Ahmed; M. B. Srinivas (VLSID, 2014)

An Iterative Logarithmic Multiplier with Improved Precision. - Syed Ershad Ahmed; Sanket Kadam; M. B. Srinivas (ARITH, 2016)

Modeling of EXG (ECG, EMG and EEG) non-idealities using MATLAB. - Mahesh Kumar Adimulam; M. B. Srinivas (CISP-BMEI, 2016)

An Efficient Design Methodology for CNFET Based Ternary Logic Circuits. - Chetan Vudadha; P. Sai Phaneendra; M. B. Srinivas (iNIS, 2016)

A Hybrid Energy Efficient Digital Comparator. - Syed Ershad Ahmed; S. Sweekruth Srinivas; M. B. Srinivas (VLSID, 2016)

A Soft Computing Approach for Data Routing in Hospital Area Networks (HAN). - Rakhee; M. B. Srinivas (Int. J. Bus. Data Commun. Netw., 2016)

A low power, low noise Programmable Analog Front End (PAFE) for biopotential measurements. - Mahesh Kumar Adimulam; Adimulam Divya; K. Tejaswi; M. B. Srinivas (EMBC, 2017)

A 0.32 µW, 76.8 dB SNDR Programmable Gain Instrumentation Amplifier for Bio-Potential Signal Processing Applications. - Mahesh Kumar Adimulam; Krishna Kumar Movva; K. Kolluru; M. B. Srinivas (ISVLSI, 2017)

Ultra Low Power Programmable Wireless ExG SoC Design for IoT Healthcare System. - Mahesh Kumar Adimulam; M. B. Srinivas (MobiHealth, 2017)

Optimizing the Reversible Circuits Using Complementary Control Line Transformation. - Sai Phaneendra Parlapalli; Chetan Vudadha; M. B. Srinivas (RC, 2017)

An ESOP Based Cube Decomposition Technique for Reversible Circuits. - Sai Phaneendra Parlapalli; Chetan Vudadha; M. B. Srinivas (RC, 2017)

A low power, programmable 12-bit two step SAR-flash ADC for signal processing applications. - Mahesh Kumar Adimulam; Krishna Kumar Movva; M. B. Srinivas (SoCC, 2017)

T2A: Analog and RF circuits. - M. B. Srinivas (SoCC, 2017)

A low power, programmable bias inverter quantizer (BIQ) flash ADC. - Mahesh Kumar Adimulam; Krishna Kumar Movva; Amit Kapoor; M. B. Srinivas (VLSI-SoC, 2017)

A Switched-Capacitor Amplifier with True Rail-to-Rail Input Range without Using a Rail-to-Rail Op-Amp. - Anjali Gopinath; Ravi Kumar Adusumalli; Veeresh Babu Vulligaddala; M. B. Srinivas (VLSID, 2017)

Design of Software and Data Analytics for Self-Powered Wireless IoT Devices. - Linga Reddy Cenkeramaddi; Ashish Goyal; Asheesh Bhuria; M. B. Srinivas; Soumya J. (iSES, 2018)

Design Methodologies for Ternary Logic Circuits. - Chetan Vudadha; M. B. Srinivas (ISMVL, 2018)

An Ultra Low Power, 10-Bit Two-Step Flash ADC for Signal Processing Applications. - Mahesh Kumar Adimulam; Amit Kapoor; Sreehari Veeramachaneni; M. B. Srinivas (VLSID, 2018)

Nonlinear Sequence Transformation-Based Continuous-Time Wavelet Filter Approximation. - Goutham Makkena; M. B. Srinivas (Circuits Syst. Signal Process., 2018)

Improved designs of digit-by-digit decimal multiplier. - Syed Ershad Ahmed; Ch. Santosh Varma; M. B. Srinivas (Integr., 2018)

A Digitally Calibrated Bandgap Reference With 0.06% Error for Low-Side Current Sensing Application. - Veeresh Babu Vulligaddala; Ravikumar Adusumalli; Sudhakar Singamala; M. B. Srinivas (IEEE J. Solid State Circuits, 2018)

Energy efficient design of CNFET-based multi-digit ternary adders. - Chetan Vudadha; Sai Phaneendra Parlapalli; M. B. Srinivas (Microelectron. J., 2018)

Synthesis of Ternary Logic Circuits Using 2: 1 Multiplexers. - Chetan Vudadha; Ajay Surya; Saurabh Agrawal; M. B. Srinivas (IEEE Trans. Circuits Syst. I Regul. Pap., 2018)

Levin's Transformation-based Continuous-Time Linear-Phase Selective Filters. - Goutham Makkena; M. B. Srinivas (Circuits Syst. Signal Process., 2019)

A frequency domain beamspace adaptive receive beamformer for ultrasound imaging systems: phantom simulation results. - Avinash S. Vaidya; M. B. Srinivas (Signal Image Video Process., 2019)

An Improved Logarithmic Multiplier for Media Processing. - Syed Ershad Ahmed; M. B. Srinivas (J. Signal Process. Syst., 2019)

Temperature Aware Adaptations for Improved Read Reliability in STT-MRAM Memory Subsystem. - Saravanan Sethuraman; Venkata Kalyan Tavva; Karthick Rajamani; Chitra K. Subramanian; Kyu-Hyoun Kim; Hillery C. Hunter; M. B. Srinivas (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

A 7-Cell, Stackable, Li-Ion Monitoring and Active/Passive Balancing IC With In-Built Cell Balancing Switches for Electric and Hybrid Vehicles. - Veeresh Babu Vulligaddala; Sandeep Vernekar; Sudhakar Singamala; Ravi Kumar Adusumalli; Vijay Ele; Manfred Brandl; M. B. Srinivas (IEEE Trans. Ind. Informatics, 2020)

Object Classification Technique for mmWave FMCW Radars using Range-FFT Features. - Jyoti Bhatia; Aveen Dayal; Ajit Jha; Santosh Kumar Vishvakarma; Soumya J.; M. B. Srinivas; Phaneendra K. Yalavarthy; Abhinav Kumar 001; V. Lalitha 001; Sagar Koorapati; Linga Reddy Cenkeramaddi (COMSNETS, 2021)

'Glaucoma - Automating the Cup-to-Disc Ratio Estimation in Fundus Images by Combining Random Walk Algorithm with Otsu Thresholding'. - Kotturi Venkata SaiTeja; Ponduru Manoj Kumar; Punnamraju Sarath Chandra; N. K. Jisy; Md. Hasnat Ali; M. B. Srinivas (NER, 2021)

Consumer Technology-Based Solutions for COVID-19. - Himanshu Thapliyal; Katina Michael; Saraju P. Mohanty; M. B. Srinivas; Madhavi K. Ganapathiraju (IEEE Consumer Electron. Mag., 2021)

Architecture slack exploitation for phase classification and performance estimation in server-class processors. - Diyanesh Chinnakkonda; Karthick Rajamani; M. B. Srinivas (J. Parallel Distributed Comput., 2022)

Optimization of Reversible Circuits Using Gate Pair Classification. - P. Sai Phaneendra; Chetan Vudadha; M. B. Srinivas (SN Comput. Sci., 2022)

Techniques to Improve Write and Retention Reliability of STT-MRAM Memory Subsystem. - Saravanan Sethuraman; Venkata Kalyan Tavva; M. B. Srinivas (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

A 12-bit, 1.1-GS/s, Low-Power Flash ADC. - Mahesh Kumar Adimulam; M. B. Srinivas (IEEE Trans. Very Large Scale Integr. Syst., 2022)

Hand gestures recognition using edge computing system based on vision transformer and lightweight CNN. - Khushi Gupta; Arshdeep Singh; Sreenivasa Reddy Yeduri; M. B. Srinivas; Linga Reddy Cenkeramaddi (J. Ambient Intell. Humaniz. Comput., 2023)

SNN-LIF Model for Glaucoma Classification. - Harshiv Chandra; Akash Ghosh; Rahul Singh; M. B. Srinivas (AICAS, 2024)

Bistable Physically Unclonable Function with Dynamic Threshold Voltage. - Sesibhushana Rao Bommana; Sreehari Veeramachaneni; M. B. Srinivas (MWSCAS, 2024)

Early detection of glaucoma: feature visualization with a deep convolutional network. - N. K. Jisy; Md. Hasnat Ali; Sirisha Senthil; M. B. Srinivas (Comput. methods Biomech. Biomed. Eng. Imaging Vis., 2024)

Addressing Adversarial Attacks in IoT Using Deep Learning AI Models. - Sesibhushana Rao Bommana; Sreehari Veeramachaneni; Syed Ershad Ahmed; M. B. Srinivas (IEEE Access, 2025)