Low-Power Hybrid 1-Bit Full-Adder Circuit for Energy Efficient Arithmetic Applications. - M. C. Parameshwara; H. C. Srinivasaiah (J. Circuits Syst. Comput., 2017)

Approximate Full Adders for Energy Efficient Image Processing Applications. - M. C. Parameshwara (J. Circuits Syst. Comput., 2021)

An Area-Efficient Majority Logic-Based Approximate Adders with Low Delay for Error-Resilient Applications. - M. C. Parameshwara; Naeem Maroof (Circuits Syst. Signal Process., 2022)

Defects of quantum dot cellular automata computing devices: An extensive review, evaluation, and future directions. - Angshuman Khan; M. C. Parameshwara; Rajeev Arya 001 (Microprocess. Microsystems, 2023)

Modified LMS Beamformer for Interference Rejection. - R. S. Rekha; M. C. Parameshwara; Veerendra Dakulagi (Wirel. Pers. Commun., 2023)

Reconfigurable lower-part approximate adder with error-tolerant application: an approach using QCA computing. - Angshuman Khan; M. C. Parameshwara; Naeem Maroof (Int. J. Ad Hoc Ubiquitous Comput., 2024)

Reversible quantum circuits for approximate computing with image processing application. - S. Nitya; Angshuman Khan; M. C. Parameshwara; M. Nagabhushanam (Signal Image Video Process., 2025)