Implication and Evaluation Techniques for Proving Fault Equivalence. - M. Enamul Amyeen; W. Kent Fuchs; Irith Pomeranz; Vamsi Boppana (VTS, 1999)

Fault Equivalence Identification Using Redundancy Information and Static and Dynamic Extraction. - M. Enamul Amyeen; W. Kent Fuchs; Irith Pomeranz; Vamsi Boppana (VTS, 2001)

Theorems for Efficient Identification of Indistinguishable Fault Pairs in Synchronous Sequential Circuits. - M. Enamul Amyeen; Irith Pomeranz; W. Kent Fuchs (VTS, 2002)

Concurrent Execution of Diagnostic Fault Simulation and Equivalence Identification During Diagnostic Test Generation. - Xiaoming Yu; M. Enamul Amyeen; Srikanth Venkataraman; Ruifeng Guo; Irith Pomeranz (VTS, 2003)

Fault equivalence identification in combinational circuits using implication and evaluation techniques. - M. Enamul Amyeen; W. Kent Fuchs; Irith Pomeranz; Vamsi Boppana (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003)

Evaluation of the Quality of N-Detect Scan ATPG Patterns on a Processor. - M. Enamul Amyeen; Srikanth Venkataraman; Ajay Ojha; Sangbong Lee (ITC, 2004)

Defect Diagnosis Based on Pattern-Dependent Stuck-At Faults. - Irith Pomeranz; Srikanth Venkataraman; Sudhakar M. Reddy; M. Enamul Amyeen (VLSI Design, 2004)

An Experimental Study of N-Detect Scan ATPG Patterns on a Processor. - Srikanth Venkataraman; Srihari Sivaraj; M. Enamul Amyeen; Sangbong Lee; Ajay Ojha; Ruifeng Guo (VTS, 2004)

Improving Precision Using Mixed-level Fault Diagnosis. - M. Enamul Amyeen; Debashis Nayak; Srikanth Venkataraman (ITC, 2006)

Evaluation of Test Metrics: Stuck-at, Bridge Coverage Estimate and Gate Exhaustive. - Ruifeng Guo; Subhasish Mitra; M. Enamul Amyeen; Jinkyu Lee; Srihari Sivaraj; Srikanth Venkataraman (VTS, 2006)

Dominance Based Analysis for Large Volume Production Fail Diagnosis. - Bharath Seshadri; Irith Pomeranz; Srikanth Venkataraman; M. Enamul Amyeen; Sudhakar M. Reddy (VTS, 2006)

Testing for systematic defects based on DFM guidelines. - Dongok Kim; M. Enamul Amyeen; Srikanth Venkataraman; Irith Pomeranz; Swagato Basumallick; Berni Landau (ITC, 2007)

Using Scan-Dump Values to Improve Functional-Diagnosis Methodology. - Vishnu C. Vimjam; M. Enamul Amyeen; Ruifeng Guo; Srikanth Venkataraman; Michael S. Hsiao; Kai Yang (VTS, 2007)

Prioritizing the Application of DFM Guidelines Based on the Detectability of Systematic Defects. - Dongok Kim; Irith Pomeranz; M. Enamul Amyeen; Srikanth Venkataraman (ATS, 2008)

Microprocessor system failures debug and fault isolation methodology. - M. Enamul Amyeen; Srikanth Venkataraman; Mun Wai Mak (ITC, 2009)

Defect diagnosis based on DFM guidelines. - Dongok Kim; Irith Pomeranz; M. Enamul Amyeen; Srikanth Venkataraman (VTS, 2010)

Logic BIST silicon debug and volume diagnosis methodology. - M. Enamul Amyeen; Andal Jayalakshmi; Srikanth Venkataraman; Sundar V. Pathy; Ewe C. Tan (ITC, 2011)

Built-in generation of functional broadside tests considering primary input constraints. - Bo Yao 002; Irith Pomeranz; Srikanth Venkataraman; M. Enamul Amyeen (ACM Great Lakes Symposium on VLSI, 2014)

Innovative practices session 5C: Advancements in test -keeping moore moving! - M. Enamul Amyeen (VTS, 2015)

A Joint Diagnostic Test Generation Procedure with Dynamic Test Compaction. - M. Enamul Amyeen; Irith Pomeranz; Srikanth Venkataraman (ATS, 2016)

A novel diagnostic test generation methodology and its application in production failure isolation. - M. Enamul Amyeen; Dongok Kim; Maheshwar Chandrasekar; Mohammad Noman; Srikanth Venkataraman; Anurag Jain; Neha Goel; Ramesh Sharma (ITC, 2016)

Diagnostic resolution improvement through learning-guided physical failure analysis. - Carlston Lim; Yang Xue; Xin Li 001; Ronald D. Blanton; M. Enamul Amyeen (ITC, 2016)

Reduction of diagnostic fail data volume and tester time using a dynamic N-cover algorithm. - Shraddha Bodhe; M. Enamul Amyeen; Clariza Galendez; Houston Mooers; Irith Pomeranz; Srikanth Venkataraman (VTS, 2016)

Diagnostic Fail Data Minimization Using an N-Cover Algorithm. - Shraddha Bodhe; M. Enamul Amyeen; Irith Pomeranz; Srikanth Venkataraman (IEEE Trans. Very Large Scale Integr. Syst., 2016)

Test reordering for improved scan chain diagnosis using an enhanced defect diagnosis procedure. - Srikanth Venkataraman; Irith Pomeranz; Shraddha Bodhe; M. Enamul Amyeen (ITC, 2017)

Test Modification for Reduced Volumes of Fail Data. - Irith Pomeranz; M. Enamul Amyeen; Srikanth Venkataraman (ACM Trans. Design Autom. Electr. Syst., 2017)

Reordering Tests for Efficient Fail Data Collection and Tester Time Reduction. - Shraddha Bodhe; Irith Pomeranz; M. Enamul Amyeen; Srikanth Venkataraman (IEEE Trans. Very Large Scale Integr. Syst., 2017)

Improving the Resolution of Multiple Defect Diagnosis by Removing and Selecting Tests. - Naixing Wang; Irith Pomeranz; Brady Benware; M. Enamul Amyeen; Srikanth Venkataraman (DFT, 2018)

Hybrid Pass/Fail and Full Fail Data for Reduced Fail Data Volume. - Irith Pomeranz; M. Enamul Amyeen (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021)

Logic Diagnosis with Hybrid Fail Data. - Irith Pomeranz; M. Enamul Amyeen (ACM Trans. Design Autom. Electr. Syst., 2021)

Using Fault Detection Tests to Produce Diagnostic Tests Targeting Large Sets of Candidate Faults. - Hari Addepalli; Irith Pomeranz; M. Enamul Amyeen; Suriyaprakash Natarajan; Arani Sinha; Srikanth Venkataraman (ATS, 2022)

Generating Storage-Aware Test Sets Targeting Several Fault Models. - Hari Addepalli; Irith Pomeranz; M. Enamul Amyeen; Suriyaprakash Natarajan; Arani Sinha; Srikanth Venkataraman (ISVLSI, 2024)