1Mbit 1T1C 3D DRAM with Monolithically Stacked One Planar FET and Two Vertical FET Heterogeneous Oxide Semiconductor layers over Si CMOS. - Yuki Okamoto; Yusuke Komura; Toshiki Mizuguchi; Toshihiko Saito; Minato Ito; K. Kimura; Tatsuya Onuki; Yoshinori Ando; Hiromi Sawai; Tsutomu Murakawa; Hitoshi Kunitake; Takanori Matsuzaki; et al. (VLSI Technology and Circuits, 2023)