Cache-based pipeline architecture in the Hitachi H32/200 32-bit microprocessor. - Tadahiko Nishimukai; Hideo Inayoshi; Kikuko Takagi; Kazuhiko Iwasaki; Ikuya Kawasaki; M. Hanawa; Takeshi Okada (ICCD, 1988)

On-Chip Multiple Superscalar Processors with Secondary Cache Memories. - M. Hanawa; Tadahiko Nishimukai; O. Nishii; Masato Suzuki; Kazuo Yano; Mitsuru Hiraki; Shoji Shukuri; Takashi Nishida (ICCD, 1991)

3.3-V BiCMOS circuit techniques for 250-MHz RISC arithmetic modules. - Kazuo Yano; Mitsuru Hiraki; Shoji Shukuri; M. Hanawa; Masato Suzuki; S. Morita; A. Kawamata; Nagatoshi Ohki; Takashi Nishida; Koichi Seki (IEEE J. Solid State Circuits, 1992)