Emotion recognition based on vertical cross correlation sequence of facial expression images. - M. Imtiaz Rashid; Mohd. Hasan; N. Yeasmin; Celia Shahnaz; Shaikh Anowarul Fattah; Wei-Ping Zhu 001; M. Omair Ahmed (MWSCAS, 2017)

Micro-architecture Tuning for Dynamic Frequency Scaling in Coarse-Grain Runtime Reconfigurable Arrays with Adaptive Clock Domain Support. - Qilin Si; M. Imtiaz Rashid; Benjamin Carrión Schäfer (ISVLSI, 2021)

True Random Number Generation Using Latency Variations of FRAM. - M. Imtiaz Rashid; Farah Ferdaus; Bashir M. Sabquat Bahar Talukder; Paul Henny; Aubrey N. Beal; Md. Tauhidur Rahman 001 (IEEE Trans. Very Large Scale Integr. Syst., 2021)

Improving the Quality of Hardware Accelerators through automatic Behavioral Input Language Conversion in HLS. - M. Imtiaz Rashid; Benjamin Carrión Schäfer (ASP-DAC, 2022)

Fast Parallel High-Level Synthesis Design Space Explorer: Targeting FPGAs to accelerate ASIC Exploration. - M. Imtiaz Rashid; Benjamin Carrion Schafer (ACM Great Lakes Symposium on VLSI, 2022)

Modernizing Hardware Circuits through High-Level Synthesis. - Md. Imtiaz Rashid; Qilin Si; Benjamin Carrión Schäfer (ISCAS, 2022)

MIRROR: MaxImizing the Re-usability of RTL thrOugh RTL to C CompileR. - Md. Imtiaz Rashid; Benjamin Carrion Schafer (DATE, 2023)

CERTIFY: AutomatiC MEasuRing The QualIty oF High-Level SYnthesis. - M. Imtiaz Rashid; Amir H. Torabi; Benjamin Carrión Schäfer (ISCAS, 2023)

Fast and Inexpensive High-Level Synthesis Design Space Exploration: Machine Learning to the Rescue. - Md. Imtiaz Rashid; Benjamin Carrion Schafer (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

Making Legacy Hardware Robust against Side Channel Attacks via High-Level Synthesis. - Md. Imtiaz Rashid; Benjamin Carrión Schäfer (ASP-DAC, 2025)

Robust and Efficient RTL to C Compiler Optimized for High-Level Synthesis. - Md. Imtiaz Rashid; Benjamin Carrion Schafer (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)