An Ultra-Low Voltage Auger-Recombination Enhanced Hot Hole Injection Scheme in Implementing a 3 Bits per Cell e-DRAM CIM Macro for Inference Accelerator. - T. C. Kao; M. J. Huang; Y. R. Liu; Y. K. Wang; J. C. Guo; Steve S. Chung (VLSI Technology and Circuits, 2024)

Resistive-Gate RAM: An 1TnR Architecture Feasible for Scaling Beyond 16nm CMOS Generation. - C. H. Sung; M. J. Huang; Y. J. Li; Y. T. Yang; Y. R. Liu; P. H. Shih; J. C. Guo; Steve S. Chung (IRPS, 2025)