Optimization of low temperature silicon nitride processes for improvement of device performance. - E. Sleeckx; Marc Schaekers; X. Shi; E. Kunnen; B. Degroote; M. Jurczak; Muriel de Potter de ten Broeck; E. Augendre (Microelectron. Reliab., 2005)

Layout options for stability tuning of SRAM cells in multi-gate-FET technologies. - Florian Bauer; Klaus von Arnim; Christian Pacha; Thomas Schulz; Michael Fulde; Axel Nackaerts; M. Jurczak; Wade Xiong; K. T. San; C. Rinn Cleavelin; Klaus Schruefer; Georg Georgakos; et al. (ESSCIRC, 2007)

Optimization of HfSiON using a design of experiment (DOE) approach on 0.45 V Vt Ni-FUSI CMOS transistors. - A. Rothschild; R. Mitsuhashi; Christoph Kerner; X. Shi; J. L. Everaert; L. Date; Thierry Conard; Olivier Richard; C. Vrancken; R. Verbeeck; Anabela Veloso; A. Lauwers; et al. (Microelectron. Reliab., 2007)

On the correlation between the retention time of FBRAM and the low-frequency noise of UTBOX SOI nMOSFETs. - Eddy Simoen; Marc Aoulaiche; Anabela Veloso; M. Jurczak; Cor Claeys; L. Mendes Almeida; Maria Glória Caño de Andrade; A. Luque Rodriguez; J. A. Jimenez Tejada; Christian Caillat; Pierre Fazan (ESSDERC, 2012)

Highly reliable TaOx ReRAM with centralized filament for 28-nm embedded application. - Yukio Hayakawa; Atsushi Himeno; Ryutaro Yasuhara; W. Boullart; E. Vecchio; T. Vandeweyer; T. Witters; D. Crotti; M. Jurczak; S. Fujii; S. Ito; Y. Kawashima; et al. (VLSIC, 2015)