Memory Based Multiplier Design in Custom and FPGA Implementation. - M. Mohamed Asan Basiri; S. K. Noor Mahammad (ISI (1), 2014)

An Efficient Hardware-Based Higher Radix Floating Point MAC Design. - M. Mohamed Asan Basiri; Sk. Noor Mahammad (ACM Trans. Design Autom. Electr. Syst., 2014)

Configurable Folded IIR Filter Design. - M. Mohamed Asan Basiri; Sk. Noor Mahammad (IEEE Trans. Circuits Syst. II Express Briefs, 2015)

Hardware optimizations for crypto implementations (Invited paper). - M. Mohamed Asan Basiri; Sandeep K. Shukla (VDAT, 2016)

An Efficient VLSI Architecture for Discrete Hadamard Transform. - M. Mohamed Asan Basiri; S. K. Noor Mahammad (VLSID, 2016)

Multi-mode parallel and folded VLSI architectures for 1D-fast Fourier transform. - M. Mohamed Asan Basiri; Sk. Noor Mahammad (Integr., 2016)

An efficient VLSI architecture for lifting based 1D/2D discrete wavelet transform. - M. Mohamed Asan Basiri; Sk. Noor Mahammad (Microprocess. Microsystems, 2016)

High speed multiplexer design using tree based decomposition algorithm. - M. Mohamed Asan Basiri; Sk. Noor Mahammad (Microelectron. J., 2016)

Flexible Composite Galois Field GF((2^m)^2) Multiplier Designs. - M. Mohamed Asan Basiri; Sandeep K. Shukla (VDAT, 2017)

High Performance Integer DCT Architectures for HEVC. - M. Mohamed Asan Basiri; Sk. Noor Mahammad (VLSID, 2017)

Quadruple throughput fixed point quarter precision multiply accumulate circuit design. - M. Mohamed Asan Basiri; S. K. Noor Mohammad (IET Comput. Digit. Tech., 2017)

Flexible VLSI architectures for Galois field multipliers. - M. Mohamed Asan Basiri; Sandeep K. Shukla (Integr., 2017)

Efficient Hardware-Software Codesigns of AES Encryptor and RS-BCH Encoder. - M. Mohamed Asan Basiri; Sandeep K. Shukla (VDAT, 2018)

An Efficient VLSI Architecture for Convolution Based DWT Using MAC. - M. Mohamed Asan Basiri; Sk. Noor Mahammad (VLSID, 2018)

Low power hardware implementations for network packet processing elements. - M. Mohamed Asan Basiri; Sandeep K. Shukla (Integr., 2018)

Formal Hardware Verification of InfoSec Primitives. - M. Mohamed Asan Basiri; Sandeep K. Shukla (ISVLSI, 2019)

Flexible Adaptive FIR Filter Designs Using LMS Algorithm. - M. Mohamed Asan Basiri (VDAT, 2019)

Asynchronous Hardware Design for Floating Point Multiply-Accumulate Circuit. - M. Mohamed Asan Basiri (VDAT, 2019)

Asynchronous hardware implementations for crypto primitives. - M. Mohamed Asan Basiri; Sandeep K. Shukla (Microprocess. Microsystems, 2019)

LFSR based versatile divider architectures for BCH and RS error correction encoders. - M. Mohamed Asan Basiri; Sandeep K. Shukla (Microprocess. Microsystems, 2019)

Discrete Orthogonal Multi-transform on Chip (DOMoC). - M. Mohamed Asan Basiri; Sk. Noor Mahammad (J. Signal Process. Syst., 2019)

Reconfigurable Hardware Design for Polynomial Galois Field Arithmetic Operations. - Hariveer Inumarty; M. Mohamed Asan Basiri (VDAT, 2020)

Efficient VLSI architectures of lifting based 3D discrete wavelet transform. - M. Mohamed Asan Basiri (IET Comput. Digit. Tech., 2020)

Hardware based Entropy Calculation in Crypto Applications. - M. Mohamed Asan Basiri (iSES, 2021)

Hardware based Order Book Design in High Frequency Algo Trading. - M. Mohamed Asan Basiri (iSES, 2021)

Low Cost Hardware Design of ECC Scalar Multiplication. - Hariveer Inumarty; M. Mohamed Asan Basiri (VDAT, 2022)

Versatile Architectures of Artificial Neural Network with Variable Capacity. - M. Mohamed Asan Basiri (Circuits Syst. Signal Process., 2022)

Efficient VLSI architecture of 3D discrete transformation. - M. Mohamed Asan Basiri (Integr., 2022)

High Throughput Circuit Designs of Digital to Analog Converter. - M. V. D. B. Anjaneya; M. Mohamed Asan Basiri (RAIT, 2023)

High Throughput Circuit Design of Flash Type Analog to Digital Converter. - Shivalasya Chinthala; M. Mohamed Asan Basiri (RAIT, 2023)

Efficient FPGA Implementations of Lifting based DWT using Partial Reconfiguration. - M. Mohamed Asan Basiri; PVSR Bharadwaja (VLSID, 2023)

Flexible and High Throughput Designs of 4-Stage Operational Amplifier. - V. Avinash Kumar; M. Mohamed Asan Basiri (ICCCNT, 2024)

Efficient Synchronous and Asynchronous Folded Architectures of SHA-3. - G. R. Sarath Chandra Reddy; M. Mohamed Asan Basiri (ICCCNT, 2024)

Low Latency VLSI Architecture of Histogram Equalization of Images. - M. Mohamed Asan Basiri (VDAT, 2024)

Efficient VLSI Architectures of Convolution based DWT using Bit Accumulation. - M. Mohamed Asan Basiri (J. Signal Process. Syst., 2025)

High Throughput Instruction-Data Level Parallelism Based Arithmetic Hardware Accelerator. - M. Mohamed Asan Basiri (Int. J. Parallel Program., 2025)

Low Cost and High Throughput VLSI Architectures of Folded and Parallel Sorters. - M. Mohamed Asan Basiri (Circuits Syst. Signal Process., 2025)

Efficient VLSI implementations of singular value decomposition. - M. Mohamed Asan Basiri (J. Supercomput., 2025)