A Modified Genetic Algorithm for Evolution of Neural Network in Designing an Evolutionary Neuro-Hardware. - N. Mohankumar 003; B. Bhuvan; M. Nirmala Devi 001; S. Arumugam (GEM, 2008)

FPGA Realization of Activation Function for Artificial Neural Networks. - Venakata Saichand; M. Nirmala Devi 001; S. Arumugam; N. Mohankumar 003 (ISDA (3), 2008)

PSO learning on artificial neural networks. - Nisha Haridas; M. Nirmala Devi 001 (A2CWiC, 2010)

A Modified Scheme for Simultaneous Reduction of Test Data Volume and Testing Power. - P. R. Sruthi; M. Nirmala Devi 001 (VDAT, 2012)

Deterministic seed selection and pattern reduction in Logic BIST. - Ramesh Bhakthavatchalu; Sreeja Krishnan; V. Vineeth; M. Nirmala Devi 001 (VDAT, 2014)

Design and analysis of GaN HEMT based LNA with CPW matching. - S. Sarathkrishna; Karthigha Balamurugan; M. Nirmala Devi 001; M. Jayakumar 001 (WOCN, 2014)

Malicious Circuit Detection for Improved Hardware Security. - R. Bharath; G. Arun Sabari; Dhinesh Ravi Krishna; Arun Prasathe; K. Harish; N. Mohankumar 003; M. Nirmala Devi 001 (SSCC, 2015)

Detection and Diagnosis of Hardware Trojan Using Power Analysis. - Eknadh Vaddi; Karthik Gaddam; Rahul Karthik Maniam; Sai Abhishek Mallavajjala; Srinivasulu Dasari; M. Nirmala Devi 001 (SSCC, 2015)

Hardware Trojan Detection Using Effective Test Patterns and Selective Segmentation. - K. Atchuta Sashank; Hari Sivarami Reddy; P. Pavithran; M. S. Akash; M. Nirmala Devi 001 (SSCC, 2017)

A Flexible Online Checking Technique to Enhance Hardware Trojan Horse Detectability by Reliability Analysis. - Rajat Subhra Chakraborty; Samuel Pagliarini; Jimson Mathew; Sree Ranjani Rajendran; M. Nirmala Devi 001 (IEEE Trans. Emerg. Top. Comput., 2017)

Capacity Analysis of Correlated MIMO in GEOSAT Downlink Land Mobile System. - S. Jaiyant Gopal; J. Ramnarayan; S. Kirthiga; M. Jayakumar 001; M. Nirmala Devi 001; R. Gandhiraj; Subhash Chandra Bera (ICACCI, 2018)

A Novel Logical Locking Technique Against Key-Guessing Attacks. - Sree Ranjani Rajendran; M. Nirmala Devi 001 (ISED, 2018)

Analysis of Circuits for Security Using Logic Encryption. - Bandarupalli Chandini; M. Nirmala Devi 001 (SSCC, 2018)

Key Retrieval from AES Architecture Through Hardware Trojan Horse. - Sivappriya Manivannan; N. Nalla Anandakumar; M. Nirmala Devi 001 (SSCC, 2018)

Enhanced Logical Locking for a Secured Hardware IP Against Key-Guessing Attacks. - Sree Ranjani Rajendran; M. Nirmala Devi 001 (VDAT, 2018)

Hypervisor for consolidating real-time automotive control units: Its procedure, implications and hidden pitfalls. - Arun Kumar Sundar Rajan; Armin Feucht; Lothar Gamer; Idriz Smaili; M. Nirmala Devi 001 (J. Syst. Archit., 2018)

Realization of Re-configurable True Random Number Generator on FPGA. - M. Priyatharishini; M. Nirmala Devi 001 (SSCC, 2019)

Secured Hardware Design with Locker-Box Against a Key-Guessing Attacks. - R. Sree Ranjani; M. Nirmala Devi 001 (J. Low Power Electron., 2019)

Fault detection in satellite power system using convolutional neural network. - M. Ganesan; R. Lavanya; M. Nirmala Devi 001 (Telecommun. Syst., 2021)

Obviating Multiple Attacks with Enhanced Logic Locking. - Paul Anu; N. Mohankumar 003; M. Nirmala Devi 001 (IC3, 2022)

Data Augmented Hardware Trojan Detection Using Label Spreading Algorithm Based Transductive Learning for Edge Computing-Assisted IoT Devices. - Vaishnavi Sankar; M. Nirmala Devi 001; M. Jayakumar 001 (IEEE Access, 2022)

Feature-based augmentation and classification for tabular data. - Balachander Sathianarayanan; Yogesh Chandra Singh Samant; Prahalad S. Conjeepuram Guruprasad; Varshin B. Hariharan; Nirmala Devi Manickam (CAAI Trans. Intell. Technol., 2022)

Trustworthy Scan Design and Testability Using Obfuscation and Logic Locking Scheme for Wireless Network Application. - M. I. Shiny; M. Nirmala Devi 001 (Mob. Networks Appl., 2022)

Reliability Enhancement of Hardware Trojan Detection using Histogram Augmentation Technique. - Vaishnavi Sankar; Balachander Sathianarayanan; Nirmala Devi Manickam; M. Jayakumar 001 (VLSID, 2023)

Hexagonal-Triangular Combinatorial Structure Based Dual-Band Circularly Polarized Patch Antenna for GAGAN Receivers. - C. Sahana; Nirmala Devi Manickam; M. Jayakumar 001 (IEEE Access, 2023)

PUF based on chip comparison technique for trustworthy scan design data security against side channel attack. - Shiny Mukkath I.; Nirmala Devi M. 001 (Int. J. Cloud Comput., 2023)

Low Noise Amplifier at 60 GHz Using Low Loss On-Chip Inductors. - Karthigha Balamurugan; M. Nirmala Devi 001; M. Jayakumar 001 (J. Electr. Comput. Eng., 2023)