Designing high performance instruction caches in VLSI. - J. E. H. M. Bormans; Willem J. Withagen; F. P. M. Budzelaar; M. P. J. Stevens (Microprocessing and Microprogramming, 1990)

Pipelining a memory based CISC processor. - J. P. C. F. H. Smeets; Willem J. Withagen; M. P. J. Stevens (Microprocessing and Microprogramming, 1990)

System level VLSI design. - M. P. J. Stevens; F. P. M. Budzelaar (Microprocessing and Microprogramming, 1990)

Task level behavioral hardware description. - L. P. M. Benders; M. P. J. Stevens (Microprocessing and Microprogramming, 1991)

Object oriented system analysis for VLSI. - Yun-Chao Hu; Ad Verschueren; M. P. J. Stevens (Microprocessing and Microprogramming, 1991)

Compilation techniques for a high level language processor. - B. W. Watson; Willem J. Withagen; M. P. J. Stevens (Microprocessing and Microprogramming, 1991)

Task level specification and communication. - L. P. M. Benders; M. P. J. Stevens (Microprocess. Microprogramming, 1992)

TL: A system specification system. - L. P. M. Benders; M. P. J. Stevens (Microprocess. Microprogramming, 1993)

System-Level Testability of Hardware/Software Systems. - Harald P. E. Vranken; M. P. J. Stevens; M. T. M. Segers; J. H. M. M. van Rhee (ITC, 1994)

Behaviour-Preserving Transformations in SHE: A Formal Approach to Architecture Design. - Jeroen Voeten; P. H. A. van der Putten; M. P. J. Stevens (EUROMICRO, 1996)

Design-For-Debug in Hardware/Software Co-Design. - Harald P. E. Vranken; M. P. J. Stevens; M. T. M. Segers (CODES, 1997)

System Level Modelling for Hardware/Software Systems. - Jeroen Voeten; P. H. A. van der Putten; Marc Geilen; M. P. J. Stevens (EUROMICRO, 1998)

System Level Models for Real-Time Communication. - P. H. A. van der Putten; Jeroen Voeten; Marc Geilen; M. P. J. Stevens (EUROMICRO, 1999)

Object-oriented modelling and specification using SHE. - Marc Geilen; Jeroen Voeten; P. H. A. van der Putten; Leo J. van Bokhoven; M. P. J. Stevens (Comput. Lang., 2001)

Concurrent Support of Higher-Layer Protocols over WDM. - Bart D. Theelen; Jeroen Voeten; P. H. A. van der Putten; M. P. J. Stevens; Harm J. S. Dorren (Photonic Netw. Commun., 2002)

A scalable single-chip multi-processor architecture with on-chip RTOS kernel. - Bart D. Theelen; A. C. Verschueren; V. V. Reyes Suárez; M. P. J. Stevens; Antonio Núñez (J. Syst. Archit., 2003)