Pushing the Limits of Energy Efficiency for Non-Binary LDPC Decoders on GPUs and FPGAs. - Srinivasan Subramaniyan; Oscar Ferraz; M. R. Ashuthosh; Santosh Krishna; Guohui Wang; Joseph R. Cavallaro; Vítor Silva 001; Gabriel Falcão 001; Madhura Purnaprajna (SiPS, 2020)

MAPPARAT: A Resource Constrained FPGA-Based Accelerator for Sparse-Dense Matrix Multiplication. - M. R. Ashuthosh; Santosh Krishna; Vishvas Sudarshan; Srinivasan Subramaniyan; Madhura Purnaprajna (VLSID, 2022)

Enabling High-Level Design Strategies for High-Throughput and Low-Power NB-LDPC Decoders. - Srinivasan Subramaniyan; Oscar Ferraz; M. R. Ashuthosh; Santosh Krishna; Guohui Wang; Joseph R. Cavallaro; Vítor Silva 001; Gabriel Falcão 001; Madhura Purnaprajna (IEEE Des. Test, 2023)