Power efficient sequential multiplication using pre-computation. - Nima Honarmand; M. Reza Javaheri; Naser Sedaghati-Mokhtari; Ali Afzali-Kusha (ISCAS, 2006)

Verification and fault synthesis algorithm at switch-level. - M. Reza Javaheri; Reza Sedaghat; Leo Kant; Jason Zalev (Microprocess. Microsystems, 2006)

Transistor-level to gate-level comprehensive fault synthesis for n-input primitive gates. - Reza Sedaghat; Mayuri Kunchwar; Raha Abedi; M. Reza Javaheri (Microelectron. Reliab., 2006)

A Novel Delay Fault Testing Methodology for Resistive Faults in Deep Sub-micron Technologies. - M. Reza Javaheri; Reza Sedaghat (CSICC, 2008)

Multi-valued logic mapping of resistive short and open delay-fault testing in deep sub-micron technologies. - M. Reza Javaheri; Reza Sedaghat (Microelectron. Reliab., 2009)

Switch-level soft error emulation for SET-induced pulses of variable strengths. - Reza Sedaghat; M. Reza Javaheri; Prabhleen K. Kalkat; Jalal Mohammad Chikhe (Microelectron. J., 2010)

Strength violation effect on soft-error detection in sub-micron technology. - M. Reza Javaheri; Reza Sedaghat (Microelectron. Reliab., 2010)

Switch-level emulation of strength-base soft error detection. - Reza Sedaghat; M. Reza Javaheri; Prabhleen K. Kalkat; Jalal Mohammad Chikhe (Microelectron. Reliab., 2011)