Layout Level Design for Testability Strategy Applied to a CMOS Cell Library. - M. Rullán; F. C. Blom; Joan Oliver; Carles Ferrer 001 (DFT, 1993)

Layout-level design for testability rules for a CMOS cell library. - M. Rullán; F. C. Blom; Joan Oliver; Carles Ferrer 001 (EURO-DAC, 1993)

Testability enhancement using physical design rules in a CMOS cell library. - F. C. Blom; Joan Oliver; M. Rullán; Carles Ferrer 001 (Microprocess. Microprogramming, 1993)

An Approach to the Development of a IDDQ Testable Cell Library. - Carles Ferrer 001; D. Dateo; Joan Oliver; Antonio Rubio 001; M. Rullán (DFT, 1994)

Analysis of ISSQ/IDDQ Testing Implementation and Circuit Partitioning in CMOS Cell-Based Design. - M. Rullán; Carles Ferrer 001; Joan Oliver; Diego Mateo; Antonio Rubio 001 (ED&TC, 1996)