Static power minimization in current-mode circuits. - M. S. Bhat 001; H. S. Jamadagni (ASP-DAC, 2005)

An Extrinsic Method for the Synthesis of Analog Functions using Non-Linear Current-Mode Circuits. - M. S. Bhat 001; S. Rekha; H. S. Jamadagni (IICAI, 2005)

An Extrinsic Method of Evolutionary Synthesis of Multiple-Valued Arithmetic Functions using Genetic Algorithms. - M. S. Bhat 001; S. Rekha; H. S. Jamadagni (IICAI, 2005)

Power Optimization in Current Mode Circuits. - M. S. Bhat 001; H. S. Jamadagni (VLSI Design, 2005)

Extrinsic Analog Synthesis Using Piecewise Linear Current-Mode Circuits. - M. S. Bhat 001; S. Rekha; H. S. Jamadagni (VLSI Design, 2006)

Design of resolution adaptive TIQ flash ADC using AMS 0.35 µm technology. - G. Rajashekar; M. S. Bhat 001 (Int. J. Inf. Commun. Technol., 2009)

Minimization of Via-Induced Signal Reflection in On-Chip High Speed Interconnect Lines. - K. Soorya Krishna; M. S. Bhat 001 (Circuits Syst. Signal Process., 2012)

Object detection and obstacle avoidance for mobile robot using stereo camera. - R. Lagisetty; N. K. Philip; R. Padhi; M. S. Bhat 001 (CCA, 2013)

Low Energy and Area Efficient Nonbinary Capacitor Array Based SAR ADC. - D. N. Jagadish; M. S. Bhat 001 (ISED, 2014)

A Low Voltage Inverter Based Differential Amplifier for Low Power Switched Capacitor Applications. - D. N. Jagadish; M. S. Bhat 001 (ISED, 2014)

GSM and GUI Based Remote Data Logging System. - Sadeque Reza Khan; Rajsekhar Kr. Nath; M. S. Bhat 001 (ISED, 2014)

Inductive Tuned High Isolation RF MEMS Capacitive Shunt Switches. - E. S. Shajahan; M. S. Bhat 001; B. Chenna Reddy (ISED, 2014)

Design of a triple band-notched circular monopole antenna for UWB applications. - B. Chenna Reddy; E. S. Shajahan; M. S. Bhat 001 (WOCN, 2014)

Despeckling low SNR, low contrast ultrasound images via anisotropic level set diffusion. - A. A. Bini; M. S. Bhat 001 (Multidimens. Syst. Signal Process., 2014)

A nonlinear level set model for image deblurring and denoising. - A. A. Bini; M. S. Bhat 001 (Vis. Comput., 2014)

Low Energy and Area Efficient Nonbinary Capacitor Array Based Successive Approximation Register Analog-to-Digital Converter. - D. N. Jagadish; M. S. Bhat 001 (J. Low Power Electron., 2015)

Analysis of implant parameters in high voltage TRIPLE RESURF LDMOS for advanced SoC applications. - B. Jhnanesh Somayaji; M. S. Bhat 001 (ISED, 2016)

Smart handheld platform for electrochemical bio sensors. - Suraj Hebbar; Vinay Kumar; M. S. Bhat 001; Navakanta Bhat (VDAT, 2016)

Design of high performance dual-gate nano-scale In0.55Ga0.45 as transistor with modified substrate geometry. - Baldeo Sharan Sharma; M. S. Bhat 001 (UEMCON, 2017)

Triple Reduced Surface Field Drain Extended MOS Device Design and Its RF Performance Evaluation for Sub-Micron RF SoC Platform. - B. Jhnanesh Somayaji; M. S. Bhat 001 (J. Low Power Electron., 2017)

High Isolation Single Pole Four Throw RF MEMS Switches for X band. - E. S. Shajahan; M. S. Bhat 001 (ISED, 2018)

14.5 fJ/conversion-step 9-bit 100-kS/s non-binary weighted dual capacitor array based area and energy efficient SAR ADC in 90 nm CMOS. - Jagadish Dasarahalli Narasimaiah; Mujoor Shankaranarayana Bhat (IET Circuits Devices Syst., 2018)

11.39 fJ/conversion-step 780 kS/s 8 bit switched capacitor-based area and energy-efficient successive approximation register ADC in 90 nm complementary metal-oxide-semiconductor. - Jagadish Dasarahalli Narasimaiah; Laxminidhi Tonse; Mujoor Sankaranarayana Bhat (IET Circuits Devices Syst., 2018)

Fabrication and characterisation of RF MEMS capacitive switches tuned for X and Ku bands. - E. S. Shajahan; M. S. Bhat 001 (Int. J. Mechatronics Autom., 2018)

Design of High Resolution Delta Sigma Modulator in 180 nm CMOS technology. - Samarth Bonthala; Yashas Uppoor; Ashika Nayak; Sreenivasulu Polineni; M. S. Bhat 001 (ISED, 2019)

A 0.3 V, 56 dB DR, 100 Hz fourth order low-pass filter for ECG acquisition system. - Sreenivasulu Polineni; G. Hanumanta Rao; S. Rekha; M. S. Bhat 001 (Microelectron. J., 2019)

A Switched Capacitor-Based SAR ADC Employing a Passive Reference Charge Sharing and Charge Accumulation Technique. - Sreenivasulu Polineni; M. S. Bhat 001; S. Rekha (Circuits Syst. Signal Process., 2020)

A 0.3-V, 2.4-nW, and 100-Hz fourth-order LPF for ECG signal processing. - G. Hanumantha Rao; Sreenivasulu Polineni; S. Rekha; M. S. Bhat 001 (Int. J. Circuit Theory Appl., 2020)

A fully differential switched-capacitor integrator based programmable resolution hybrid ADC architecture for biomedical applications. - Sreenivasulu Polineni; S. Rekha; M. S. Bhat 001 (IET Circuits Devices Syst., 2021)

CCD Sensor Based Cameras for Sustainable Streaming IoT Applications With Compressed Sensing. - Ramachandra Gambheer; M. S. Bhat 001 (IEEE Access, 2023)

Optimized Compressed Sensing for IoT: Advanced Algorithms for Efficient Sparse Signal Reconstruction in Edge Devices. - Ramachandra Gambheer; M. S. Bhat 001 (IEEE Access, 2024)