Clock rate versus IPC: the end of the road for conventional microarchitectures. - Vikas Agarwal; M. S. Hrishikesh; Stephen W. Keckler; Doug Burger (ISCA, 2000)

The Optimal Logic Depth Per Pipeline Stage is 6 to 8 FO4 Inverter Delays. - M. S. Hrishikesh; Doug Burger; Stephen W. Keckler; Premkishore Shivakumar; Norman P. Jouppi; Keith I. Farkas (ISCA, 2002)

Static energy reduction techniques for microprocessor caches. - Heather Hanson; M. S. Hrishikesh; Vikas Agarwal; Stephen W. Keckler; Doug Burger (IEEE Trans. Very Large Scale Integr. Syst., 2003)