From Equation to VHDL: Using Rewriting Logic for Automated Function Generation. - Carlos Morra; M. Sackmann; Sunil Shukla; Jürgen Becker 001; Reiner W. Hartenstein (FPL, 2006)

Using Rewriting Logic to Generate Different Implementations of Polynomial Approximations in Coarse-Grained Architectures. - Carlos Morra; M. Sackmann; Jürgen Becker 001; Reiner W. Hartenstein (ReCoSoC, 2006)