Array-Specific Dataflow Caches for High-Level Synthesis of Memory-Intensive Algorithms on FPGAs. - Giovanni Brignone; M. Usman Jamal; Mihai T. Lazarescu; Luciano Lavagno (IEEE Access, 2022)

A Graph Neural Network Model for Fast and Accurate Quality of Result Estimation for High-Level Synthesis. - M. Usman Jamal; Zhuowei Li 006; Mihai T. Lazarescu; Luciano Lavagno (IEEE Access, 2023)

LESS: Low-Power Energy-Efficient Subgraph Isomorphism on FPGA. - Roberto Bosio; Giovanni Brignone; Filippo Minnella; M. Usman Jamal; Luciano Lavagno (DATE, 2024)