FPGA-based parallel architecture for PID control algorithm and HDL co-simulation. - T. Ananthan; M. V. Vaidyan (Int. J. Embed. Syst., 2013)

A Reconfigurable Parallel Hardware Implementation of the Self-Tuning Regulator. - T. Ananthan; M. V. Vaidyan (ACM Trans. Reconfigurable Technol. Syst., 2013)

An FPGA-based parallel architecture for on-line parameter estimation using the RLS identification algorithm. - T. Ananthan; M. V. Vaidyan (Microprocess. Microsystems, 2014)

Estimator based controllers for hybrid systems with uncertainties - an experimental validation. - Shijoh Vellayikot; M. V. Vaidyan (ICACCI, 2015)