DIGIMOD: A Tool to Implement FPGA-Based Digital IF and Baseband Modems. - José Marín-Roig; Vicente Torres-Carot; Ma José Canet; Asuncion Perez-Pascual; Trinidad Sansaloni; Francisco Cardells-Tormo; Fabian Angarita; Felip Vicedo; Vicenc Almenar-Terre; Javier Valls-Coquillat (FPL, 2003)

Hardware Design of a FPGA-Based Synchronizer for Hiperlan/2. - Ma José Canet; Felip Vicedo; Vicenc Almenar-Terre; Javier Valls-Coquillat; Eduardo R. de Lima (FPL, 2004)

A common FPGA based synchronizer architecture for Hiperlan/2 and IEEE 802.11a WLAN systems. - Ma José Canet; Felip Vicedo; Vicenç Almenar; Javier Valls; Eduardo R. de Lima (PIMRC, 2004)

Analysis and Contrast Between STC and Spatial Diversity Techniques for OFDM WLAN with Channel Estimation. - Eduardo R. de Lima; Santiago J. Flores; Vicenc Almenar-Terre; Ma José Canet (SAPIR, 2004)

Performance evaluation of fine time synchronizers for WLANs. - Ma José Canet; Ian J. Wassell; Javier Valls; Vicenç Almenar (EUSIPCO, 2005)

Improvement of a time synchronization algorithm for IEEE 802.11a/g WLAN standard. - Ma José Canet; Vicenç Almenar; Santiago J. Flores; Javier Valls (EUSIPCO, 2007)

Reduction of power consumption in a Viterbi Decoder for OFDM-WLAN. - Fabian Angarita Preciado; María José Canet; Trinidad Sansaloni Balaguer; Vicenc Almenar-Terre; Javier Valls-Coquillat (ICECS, 2007)

Time Synchronization for the IEEE 802.11a/g WLAN Standard. - María José Canet; Vicenç Almenar; José Marín-Roig; Javier Valls (PIMRC, 2007)

64-QAM 4×4 MIMO decoders based on Successive Projection Algorithm. - José Marín-Roig; Vicenç Almenar; Javier Valls; Ma José Canet (ICECS, 2008)

Efficient Mapping of CORDIC Algorithm for OFDM-Based WLAN. - Fabian Angarita; Ma José Canet; T. Sansaloni; A. Perez-Pascual; Javier Valls (J. Signal Process. Syst., 2008)

Architectures for the Implementation of a OFDM-WLAN Viterbi Decoder. - Fabian Angarita; Ma José Canet; T. Sansaloni; Javier Valls; Vicenc Almenar-Terre (J. Signal Process. Syst., 2008)

Power Consumption Reduction in a Viterbi Decoder for OFDM-WLAN. - Fabian Angarita; Ma José Canet; Trinidad Sansaloni; Vicenç Almenar; Javier Valls (J. Circuits Syst. Comput., 2009)

Decoder for an enhanced serial generalized bit flipping algorithm. - Francisco Garcia-Herrero; María José Canet; Javier Valls (ICECS, 2012)

Serial Symbol-Reliability Based Algorithm for Decoding Non-Binary LDPC Codes. - Francisco Garcia-Herrero; María José Canet; Javier Valls; Mark F. Flanagan (IEEE Commun. Lett., 2012)

FPGA implementation of an OFDM-based WLAN receiver. - María José Canet; Javier Valls; Vicenç Almenar; José Marín-Roig (Microprocess. Microsystems, 2012)

High-Throughput Interpolator Architecture for Low-Complexity Chase Decoding of RS Codes. - Francisco Garcia-Herrero; María José Canet; Javier Valls; Pramod Kumar Meher (IEEE Trans. Very Large Scale Integr. Syst., 2012)

Improved Sliced Message Passing Architecture for High Throughput Decoding of LDPC Codes. - Fabian Angarita; Trinidad Sansaloni; María José Canet; Javier Valls (J. Signal Process. Syst., 2012)

Low Complexity Time Synchronization Algorithm for OFDM Systems with Repetitive Preambles. - María José Canet; Vicenc Almenar-Terre; Santiago J. Flores; Javier Valls (J. Signal Process. Syst., 2012)

High-speed NB-LDPC decoder for wireless applications. - Francisco Garcia-Herrero; Ma José Canet; Javier Valls (ISPACS, 2013)

Architecture of Generalized Bit-Flipping Decoding for High-Rate Non-binary LDPC Codes. - Francisco Garcia-Herrero; María José Canet; Javier Valls (Circuits Syst. Signal Process., 2013)

Nonbinary LDPC Decoder Based on Simplified Enhanced Generalized Bit-Flipping Algorithm. - Francisco Garcia-Herrero; María José Canet; Javier Valls (IEEE Trans. Very Large Scale Integr. Syst., 2014)

A 630 Mbps non-binary LDPC decoder for FPGA. - Jesus Omar Lacruz; Francisco Garcia-Herrero; Ma José Canet; Javier Valls; Asuncion Perez-Pascual (ISCAS, 2015)

High-Performance NB-LDPC Decoder With Reduction of Message Exchange. - Jesus Omar Lacruz; Francisco Garcia-Herrero; María José Canet; Javier Valls (IEEE Trans. Very Large Scale Integr. Syst., 2016)

Reduced-Complexity Nonbinary LDPC Decoder for High-Order Galois Fields Based on Trellis Min-Max Algorithm. - Jesus Omar Lacruz; Francisco Garcia-Herrero; María José Canet; Javier Valls (IEEE Trans. Very Large Scale Integr. Syst., 2016)

Soft-decision LCC Decoder Architecture with n=4 for RS(255, 239). - Vicente Torres 001; Javier Valls; María José Canet; Francisco Garcia-Herrero (NEWCAS, 2018)

A Test Vector Generation Method Based on Symbol Error Probabilities for Low-Complexity Chase Soft-Decision Reed-Solomon Decoding. - Javier Valls; Vicente Torres 001; María José Canet; Francisco Miguel Garcia-Herrero (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

Low Complexity System on Chip Design to Acquire Signals from MOS Gas Sensor Applications. - Juan B. Talens; José Pelegrí-Sebastiá; María José Canet (Sensors, 2021)

Model and Methodology to Characterize Phosphor-Based White LED Visible Light Communication Links. - Pau Salvador; Vicenç Almenar; Juan Luis Corral; Javier Valls; María José Canet (Sensors, 2023)

Hybrid POF-VLC Network Downlink in Indoor Environments. - Pau Salvador; Ma José Canet; Javier Valls; Vicenç Almenar; Juan Luis Corral (VCC, 2024)

Helping First-Year University Students to Overcome the Threshold Concept of Ohm's Law. - María José Canet; María Asunción Pérez-Pascual; Lorena Atarés; Macarena Trujillo (IEEE Trans. Educ., 2025)