A 25-Ms/s 8-bit CMOS A/D converter for embedded application. - Marcel J. M. Pelgrom; A. C. Jeannet v. Rens; Maarten Vertregt; Marcel B. Dijkstra (IEEE J. Solid State Circuits, 1994)

BiCMOS and CMOS: a long term relation. - Marcel J. M. Pelgrom; Maarten Vertregt (ICECS, 1996)

A Mixed-Signal Design Roadmap. - Ralf Brederlow; Werner Weber; Joseph Sauerer; Stéphane Donnay; Piet Wambacq; Maarten Vertregt (IEEE Des. Test Comput., 2001)

A 2.5-V 12-b 54-Msample/s 0.25-μm CMOS ADC in 1-mm2 with mixed-signal chopping and calibration. - Hendrik van der Ploeg; Gian Hoogzaad; Henk A. H. Termeer; Maarten Vertregt; Raf L. J. Roovers (IEEE J. Solid State Circuits, 2001)

A 6-b 1.6-Gsample/s flash ADC in 0.18-μm CMOS using averaging termination. - Peter C. S. Scholtens; Maarten Vertregt (IEEE J. Solid State Circuits, 2002)

A 1.8V 100mW 12-bits 80Msample/s two-step ADC in 0.18-μm CMOS. - Amir Zjajo; Hendrik van der Ploeg; Maarten Vertregt (ESSCIRC, 2003)

A 1.6 GS/s, 16 times interleaved track & hold with 7.6 ENOB in 0.12 μm CMOS [ADC applications]. - Simon M. Louwsma; Ed J. M. van Tuijl; Maarten Vertregt; Peter C. S. Scholtens; Bram Nauta (ESSCIRC, 2004)

Assessment of the merits of CMOS technology scaling for analog circuit design. - Maarten Vertregt; Peter C. S. Scholtens (ESSCIRC, 2004)

Systematic power reduction and performance analysis of mismatch limited ADC designs. - Peter C. S. Scholtens; David Smola; Maarten Vertregt (ISLPED, 2005)

A 15-bit 30-MS/s 145-mW three-step ADC for imaging applications. - Hendrik van der Ploeg; Maarten Vertregt; Marco Lammers (IEEE J. Solid State Circuits, 2006)

A Time-Interleaved Track & hold in 0.13 μm CMOS sub-sampling a 4 GHz signal with 43 dB SNDR. - Simon M. Louwsma; Ed van Tuijl; Maarten Vertregt; Bram Nauta (CICC, 2007)

A 1.35 GS/s, 10 b, 175 mW Time-Interleaved AD Converter in 0.13 µm CMOS. - Simon M. Louwsma; A. J. M. van Tuijl; Maarten Vertregt; Bram Nauta (IEEE J. Solid State Circuits, 2008)

A 0.45pJ/conv-step 1.2Gs/s 6b full-Nyquist non-calibrated flash ADC in 45nm CMOS and its scaling behavior. - Paul Veldhorst; George Goksun; Anne-Johan Annema; Bram Nauta; Berry A. J. Buter; Maarten Vertregt (ESSCIRC, 2009)

A 1.2-V 250-mW 14-b 100-MS/s Digitally Calibrated Pipeline ADC in 90-nm CMOS. - Hans Van de Vel; Berry A. J. Buter; Hendrik van der Ploeg; Maarten Vertregt; Govert J. G. M. Geelen; Edward J. F. Paulus (IEEE J. Solid State Circuits, 2009)

High performance mixed signal: Business and technology. - René Penning de Vries; Hans Rijns; Maarten Vertregt (ESSCIRC, 2010)

A forward body bias generator for digital CMOS circuits with supply voltage scaling. - Maurice Meijer; José Pineda de Gyvez; Ben Kup; Bert van Uden; Peter Bastiaansen; Marco Lammers; Maarten Vertregt (ISCAS, 2010)

A narrow-to-wideband scrambling technique increasing software radio receiver linearity. - Fabian van Houwelingen; Ed van Tuijl; Bram Nauta; Maarten Vertregt (ESSCIRC, 2011)

Standard cell library tuning for variability tolerant designs. - Sebastien Fabrie; Juan Diego Echeverri; Maarten Vertregt; José Pineda de Gyvez (DATE, 2014)

Digital Systems Power Management for High Performance Mixed Signal Platforms. - Ajay Kapoor; Cas Groot; Gerard Villar Pique; Hamed Fatemi; Juan Diego Echeverri; Leo Sevat; Maarten Vertregt; Maurice Meijer; Vibhu Sharma; Yu Pu; José Pineda de Gyvez (IEEE Trans. Circuits Syst. I Regul. Pap., 2014)

Circuit valorization in the IC design ecosystem. - José Pineda de Gyvez; Hamed Fatemi; Maarten Vertregt (ICCAD, 2016)