Path Delay Fault Testing of a Class of Circuit-Switched Multistage Interconnection Networks. - Maciej Bellos; Dimitris Nikolos; Haridimos T. Vergos (EDCC, 1999)

Path delay fault testing of Benes multistage interconnection networks. - Haridimos T. Vergos; Maciej Bellos; Dimitris Nikolos (ICECS, 1999)

A Formal Test Set for RNS Adders and an Efficient Low Power BIST Scheme. - Haridimos T. Vergos; Dimitris Nikolos; Maciej Bellos; Costas Efstathiou (LATW, 2001)

Test Set Embedding Based on Phase Shifters. - Maciej Bellos; Dimitrios Kagaris; Dimitris Nikolos (EDCC, 2002)

Low Power Test Set Embedding Based on Phase Shifters. - Maciej Bellos; Dimitri Kagaris; Dimitris Nikolos (ISVLSI, 2003)

DV-TSE: Difference Vector Based Test Set Embedding. - Maciej Bellos; Xrysovalantis Kavousianos; Dimitris Nikolos; Dimitri Kagaris (VLSI-SOC, 2003)

Deterministic BIST for RNS Adders. - Haridimos T. Vergos; Dimitris Nikolos; Maciej Bellos; Costas Efstathiou (IEEE Trans. Computers, 2003)

Low Power Testing by Test Vector Ordering with Vector Repetition. - Maciej Bellos; Dimitris Bakalis; Dimitris Nikolos; Xrysovalantis Kavousianos (ISQED, 2004)

Scan Cell Ordering for Low Power BIST. - Maciej Bellos; Dimitris Bakalis; Dimitris Nikolos (ISVLSI, 2004)

An Efficient Test Vector Ordering Method for Low Power Testing. - Xrysovalantis Kavousianos; Dimitris Bakalis; Maciej Bellos; Dimitris Nikolos (ISVLSI, 2004)

Deterministic Test Vector Compression / Decompression Using an Embedded Processor. - Maciej Bellos; Dimitris Nikolos (EDCC, 2005)

Τεχνικές ελέγχου ορθής λειτουργίας με έμφαση στη χαμηλή κατανάλωση ισχύος - Maciej Bellos (2005)

A core generator for arithmetic cores and testing structures with a network interface. - Dimitris Bakalis; Kostas Adaos; Dimitrios Lymperopoulos; Maciej Bellos; Haridimos T. Vergos; George Alexiou; Dimitris Nikolos (J. Syst. Archit., 2006)