FPGA in Rough Set Based Core and Reduct Computation. - Tomasz Grzes; Maciej Kopczynski; Jaroslaw Stepaniuk (RSKT, 2013)

The First Step Toward Processor for Rough Set Methods. - Jaroslaw Stepaniuk; Maciej Kopczynski; Tomasz Grzes (Fundam. Informaticae, 2013)

Hardware Implementations of Rough Set Methods in Programmable Logic Devices. - Maciej Kopczynski; Jaroslaw Stepaniuk (Rough Sets and Intelligent Systems (2), 2013)

Generating Core in Rough Set Theory: Design and Implementation on FPGA. - Maciej Kopczynski; Tomasz Grzes; Jaroslaw Stepaniuk (RSEISP, 2014)

FPGA in Rough-Granular Computing: Reduct Generation. - Maciej Kopczynski; Tomasz Grzes; Jaroslaw Stepaniuk (WI-IAT (1), 2014)

Computation of Cores in Big Datasets: An FPGA Approach. - Maciej Kopczynski; Tomasz Grzes; Jaroslaw Stepaniuk (RSKT, 2015)

Hardware Supported Rough Sets Based Rules Generation for Big Datasets. - Maciej Kopczynski; Tomasz Grzes; Jaroslaw Stepaniuk (CISIM, 2016)

Core for Large Datasets: Rough Sets on FPGA. - Maciej Kopczynski; Tomasz Grzes; Jaroslaw Stepaniuk (Fundam. Informaticae, 2016)

Rough Sets Based LEM2 Rules Generation Supported by FPGA. - Maciej Kopczynski; Tomasz Grzes; Jaroslaw Stepaniuk (Fundam. Informaticae, 2016)

Hardware Supported Rule-Based Classification on Big Datasets. - Maciej Kopczynski; Tomasz Grzes; Jaroslaw Stepaniuk (IJCRS (1), 2017)

Hardware Implementation on Field Programmable Gate Array of Two-Stage Algorithm for Rough Set Reduct Generation. - Tomasz Grzes; Maciej Kopczynski (IJCRS, 2019)

Parallelized Hardware Rough Set Processor Architecture in FPGA for Core Calculation in Big Datasets. - Maciej Kopczynski; Tomasz Grzes (ICARCV, 2020)

Development of Digital Competences of Elementary School Teachers with a Life-Long Learning Approach. - Michal Czolombitko; Tomasz Grzes; Maciej Kopczynski; Urszula Kuzelewska; Anna Lupinska-Dubicka; Dorota Mozyrska; Joanna Panasiuk (CISIM, 2021)

FPGA in Core Calculation for Big Datasets. - Maciej Kopczynski (CISIM, 2021)

Hardware Rough Set Processor Parallel Architecture in FPGA for Finding Core in Big Datasets. - Maciej Kopczynski; Tomasz Grzes (J. Artif. Intell. Soft Comput. Res., 2021)

Mobile Phone as a 6DoF Motion Controller. - Maciej Kopczynski (CISIM, 2022)

FPGA supported rough set reduct calculation for big datasets. - Maciej Kopczynski; Tomasz Grzes (J. Intell. Inf. Syst., 2022)

Usage of Real-World Maps for 3D Mobile Games - Transformations and Optimizations. - Maciej Kopczynski (CISIM, 2024)

World Maps Conversions for 3D Mobile Games Working in Real-Time Environment. - Maciej Kopczynski (ISD, 2024)