5Gbits/sec, 300mV Precharge, 256b, Low Power Rhythmic SRAM. - Shital Tak; Madan Mali; Mukul S. Sutaone (ARTCom, 2009)

On-Chip Area and Test Time Effective Weak Resistive Open Defect Detection Technique for Cache Memory. - Sheetal Barekar; Madan Mali (LASCAS, 2021)

On-chip weak resistive defect diagnosis with performance enhancement in 45 nm technology static random access memory. - Sheetal Barekar; Madan Mali (Microelectron. J., 2021)