On the Convergence of Reversible Markov Chains. - Madhav P. Desai; Vasant B. Rao (SIAM J. Matrix Anal. Appl., 1993)

A characterization of the smallest eigenvalue of a graph. - Madhav P. Desai; Vasant B. Rao (J. Graph Theory, 1994)

Sizing of Clock Distribution Networks for High Performance CPU Chips. - Madhav P. Desai; Radenko Cvijetic; James Jensen (DAC, 1996)

A Systematic Technique for Verifying Critical Path Delays in a 300MHz Alpha CPU Design Using Circuit Simulation. - Madhav P. Desai; Yao-Tsung Yen (DAC, 1996)

Robust Elmore Delay Models Suitable for Full Chip Timing Verification of a 600MHz CMOS Microprocessor. - Nevine Nassif; Madhav P. Desai; Dale H. Hall (DAC, 1998)

Decomposition of Finite State Machines for Area, Delay Minimization. - Rupesh S. Shelar; Madhav P. Desai; H. Narayanan (ICCD, 1999)

A State Assignment Scheme Targeting Performance and Area. - B. N. V. Malleswara Gupta; H. Narayanan; Madhav P. Desai (VLSI Design, 1999)

Inductance Characterization of Small Interconnects Using Test-Signal Method. - Jeegar Tilak Shah; Madhav P. Desai; Sugata Sanyal (VLSI Design, 2000)

Effect Of Fringing Capacitances In Sub 100 Nm Mosfet's With High-K Gate Dielectrics. - Nihar R. Mohapatra; Arijit Dutta; Madhav P. Desai; V. Ramgopal Rao (VLSI Design, 2001)

An On-Chip Coupling Capacitance Measurement Technique. - Pratheep A. Nair; Anubhav Gupta; Madhav P. Desai (VLSI Design, 2001)

Sub-100 nm CMOS circuit performance with high-K gate dielectrics. - Nihar R. Mohapatra; Arijit Dutta; G. Sridhar; Madhav P. Desai; V. Ramgopal Rao (Microelectron. Reliab., 2001)

Impact of Technology Scaling on Metastability Performance of CMOS Synchronizing Latches. - Maryam Shojaei Baghini; Madhav P. Desai (ASP-DAC/VLSI Design, 2002)

On the connectivity in finite ad hoc networks. - Madhav P. Desai; D. Manjunath (IEEE Commun. Lett., 2002)

Detailed Analysis of FIBL in MOS Transistors with High-K Gate Dielectrics. - Nihar R. Mohapatra; Madhav P. Desai; V. Ramgopal Rao (VLSI Design, 2003)

Interconnect Delay Minimization Using a Novel Pre-Mid-Post Buffer Strategy. - Vani Prasad; Madhav P. Desai (VLSI Design, 2003)

The realization of finite state machines by decomposition and the principal lattice of partitions of a submodular function. - Madhav P. Desai; H. Narayanan; Sachin B. Patkar (Discret. Appl. Math., 2003)

Reconfigurable finite-state machine based IP lookup engine for high-speed router. - Madhav P. Desai; Ritu Gupta; Abhay Karandikar; Kshitiz Saxena; Vinayak Samant (IEEE J. Sel. Areas Commun., 2003)

A Novel Technique Towards Eliminating the Global Clock in VLSI Circuits. - Gautam Hazari; Madhav P. Desai; Apoorv Gupta; Supratik Chakraborty (VLSI Design, 2004)

A Distributed and Pipelined Controller for a Modular and Scalable Hardware Emulator. - Aditya Mittal; Madhav P. Desai (VLSI Design, 2004)

On Buffering Schemes for Long Multi-Layer Nets. - Vani Prasad; Madhav P. Desai (VLSI Design, 2004)

Variance Reduction in Monte Carlo Capacitance Extraction. - Shabbir H. Batterywala; Madhav P. Desai (VLSI Design, 2005)

On Range Matrices and Wireless Networks in d Dimensions. - Madhav P. Desai; D. Manjunath (WiOpt, 2005)

Fast DC Analysis and Its Application to Combinatorial Optimization Problems. - Gaurav Trivedi; Madhav P. Desai; H. Narayanan (VLSI Design, 2006)

On the Impact of Address Space Assignment on Performance in Systems-on-Chip. - Gautam Hazari; Madhav P. Desai; H. Kasture (VLSI Design, 2007)

AHIR: A Hardware Intermediate Representation for Hardware Generation from High-level Programs. - Sameer D. Sahasrabuddhe; Hakim Raja; Kavi Arya; Madhav P. Desai (VLSI Design, 2007)

Parallelization of DC Analysis through Multiport Decomposition. - Gaurav Trivedi; Madhav P. Desai; H. Narayanan (VLSI Design, 2007)

Learning based address mapping for improving the performance of memory subsystems. - Pratyush Kumar; Madhav P. Desai (MASCOTS, 2009)

A C-to-RTL Flow as an Energy Efficient Alternative to Embedded Processors in Digital Systems. - Sameer D. Sahasrabuddhe; Sreenivas Subramanian; Kunal P. Ghosh; Kavi Arya; Madhav P. Desai (DSD, 2010)

Bottleneck Identification Techniques Leading to Simplified Performance Models for Efficient Design Space Exploration in VLSI Memory Systems. - Gautam Hazari; Madhav P. Desai; G. Srinivas (VLSI Design, 2010)

On Cycles in Random Graphs - Madhav P. Desai (CoRR, 2010)

The Click2NetFPGA Toolchain. - Teemu Rinta-aho; Mika Karlstedt; Madhav P. Desai (USENIX ATC, 2012)

Inner Loop Optimizations in Mapping Single Threaded Programs to Hardware. - Madhav P. Desai (CoRR, 2014)

Generalized cofactors and decomposition of Boolean satisfiability problems. - Madhav P. Desai; Virendra Sule (CoRR, 2014)

Optimization of Discrete-parameter Multiprocessor Systems using a Novel Ergodic Interpolation Technique. - Neha V. Karanjkar; Madhav P. Desai (CoRR, 2014)

On the likelihood of multiple bit upsets in logic circuits. - Nanditha P. Rao; Shahbaz Sarik; Madhav P. Desai (CoRR, 2014)

A Detailed Characterization of Errors in Logic Circuits due to Single-Event Transients. - Nanditha P. Rao; Madhav P. Desai (DSD, 2015)

An Approach to Discrete Parameter Design Space Exploration of Multi-core Systems Using a Novel Simulation Based Interpolation Technique. - Neha V. Karanjkar; Madhav P. Desai (MASCOTS, 2015)

Low-Power, Low-Latency Hermite Polynomial Characterization of Heartbeats Using a Field-Programmable Gate Array. - Kartik Lakhotia; Gabriel Caffarena; Alberto Gil 001; David G. Márquez; Abraham Otero; Madhav P. Desai (IWBBIO, 2016)

Projective cofactor decompositions of Boolean functions and the satisfiability problem. - Madhav P. Desai; Virendra Sule (CoRR, 2016)

On Continuous-space Embedding of Discrete-parameter Queuing Systems. - Neha V. Karanjkar; Madhav P. Desai (CoRR, 2016)

Higher likelihood of multiple bit-flips due to neutron-induced strikes on logic gates. - Nanditha P. Rao; Madhav P. Desai (CoRR, 2016)

Neutron-induced strike: Study of multiple node charge collection in 14nm FinFETs. - Nanditha P. Rao; Madhav P. Desai (CoRR, 2017)

Quantification of the likelihood of single event multiple transients in logic circuits in bulk CMOS technology. - Nanditha P. Rao; Madhav P. Desai (Microelectron. J., 2018)

An efficient reverse-lookup table based strategy for solving the synonym and cache coherence problem in virtually indexed, virtually tagged caches. - Madhav P. Desai; Aniket Deshmukh (CoRR, 2021)

Sitar: A Cycle-based Discrete-Event Simulation Framework for Architecture Exploration. - Neha V. Karanjkar; Madhav P. Desai (SIMULTECH, 2022)

An evaluation of a microprocessor with two independent hardware execution threads coupled through a shared cache. - Madhav P. Desai (CoRR, 2023)

Efficient Parallel Simulation of Networked Synchronous Discrete-Event Systems. - Neha V. Karanjkar; Madhav P. Desai; Akhil Kushe; Anish Natekar (WSC, 2024)

Side-channel attacks and countermeasures for heart rate retrieval from ECG characterization device. - Pablo Pérez-Tirador; Madhav P. Desai; Alejandro Rodriguez; Elena Berral; Teresa Romero; Gabriel Caffarena; Ruzica Jevtic (Int. J. Inf. Sec., 2025)