Future generation supercomputers I: a paradigm for node architecture. - Nagarajan Venkateswaran; Deepak Srinivasan; Madhavan Manivannan; T. P. Ramnath Sai Sagar; Shyamsundar Gopalakrishnan; Vinoth Krishnan Elangovan; Karthik Chandrasekar 001; Prem Kumar Ramesh; Viswanath Venkatesan; Arvindakshan Babu; Sudharshan (SIGARCH Comput. Archit. News, 2007)

Future generation supercomputers II: a paradigm for cluster architecture. - Nagarajan Venkateswaran; Deepak Srinivasan; Madhavan Manivannan; T. P. Ramnath Sai Sagar; Shyamsundar Gopalakrishnan; Vinoth Krishnan Elangovan; Arvind M; Prem Kumar Ramesh; Karthik Ganesan 006; Viswanath Krishnamurthy; Sivaramakrishnan (SIGARCH Comput. Archit. News, 2007)

On the concept of simultaneous execution of multiple applications on hierarchically based cluster and the silicon operating system. - N. Venkateswaran 002; Vinoth Krishnan Elangovan; Karthik Ganesan 006; TP Ramnath Sai Sagar; Sriram Aananthakrishanan; Shreyas Ramalingam; Shyamsundar Gopalakrishnan; Madhavan Manivannan; Deepak Srinivasan; Viswanath Krishnamurthy; Karthik Chandrasekar 001; Viswanath Venkatesan; et al. (IPDPS, 2008)

Towards modeling and integrated design automation of supercomputing clusters (MIDAS). - Nagarajan Venkateswaran; Aravind Vasudevan; Balaji Subramaniam; Ravindhiran Mukundrajan; T. P. Ramnath Sai Sagar; Madhavan Manivannan; Sriram Murali; Vinoth Krishnan Elangovan (Comput. Sci. Res. Dev., 2009)

Implications of Merging Phases on Scalability of Multi-core Architectures. - Madhavan Manivannan; Ben H. H. Juurlink; Per Stenström (ICPP, 2011)

Poster: implications of merging phases on scalability of multi-core architectures. - Madhavan Manivannan; Ben H. H. Juurlink; Per Stenström (ICS, 2011)

Efficient Forwarding of Producer-Consumer Data in Task-Based Programs. - Madhavan Manivannan; Anurag Negi; Per Stenström (ICPP, 2013)

Runtime-Guided Cache Coherence Optimizations in Multi-core Architectures. - Madhavan Manivannan; Per Stenström (IPDPS, 2014)

RADAR: Runtime-assisted dead region management for last-level caches. - Madhavan Manivannan; Vassilis Papaefstathiou; Miquel Pericàs; Per Stenström (HPCA, 2016)

Towards Runtime-Assisted Cache Management for Task-Parallel Programs. - Madhavan Manivannan (2016)

Runtime-Assisted Global Cache Management for Task-Based Parallel Programs. - Madhavan Manivannan; Miquel Pericàs; Vassilis Papaefstathiou; Per Stenström (IEEE Comput. Archit. Lett., 2017)

Global Dead-Block Management for Task-Parallel Programs. - Madhavan Manivannan; Miquel Pericàs; Vassilis Papaefstathiou; Per Stenström (ACM Trans. Archit. Code Optim., 2018)

LEGaTO: Low-Energy, Secure, and Resilient Toolset for Heterogeneous Computing. - Behzad Salami 001; Konstantinos Parasyris; Adrián Cristal; Osman S. Unsal; Xavier Martorell; Paul Carpenter; Raúl de la Cruz; Leonardo Bautista-Gomez; Daniel A. Jiménez; Carlos Álvarez 001; S. Nabavi; Sergi Madonar; et al. (CoRR, 2019)

Enhancing Thread-Level Parallelism in Asymmetric Multicores using Transparent Instruction Offloading. - Jeckson Dellagostin Souza; Madhavan Manivannan; Miquel Pericàs; Antonio Carlos Schneider Beck (DAC, 2020)

LEGaTO: Low-Energy, Secure, and Resilient Toolset for Heterogeneous Computing. - Behzad Salami 001; Konstantinos Parasyris; Adrián Cristal; Osman S. Unsal; Xavier Martorell; Paul Carpenter; Raúl de la Cruz; Leonardo Bautista-Gomez; Daniel A. Jiménez; Carlos Álvarez 001; Seyed Saber Nabavi Larimi; Sergi Madonar; et al. (DATE, 2020)

Enhancing Multithreaded Performance of Asymmetric Multicores with SIMD Offloading. - Jeckson Dellagostin Souza; Madhavan Manivannan; Miquel Pericàs; Antonio Carlos Schneider Beck (DATE, 2020)

Scheduling Task-parallel Applications in Dynamically Asymmetric Environments. - Jing Chen 038; Pirah Noor Soomro; Mustafa Abduljabbar; Madhavan Manivannan; Miquel Pericàs (ICPP Workshops, 2020)

DELTA: Distributed Locality-Aware Cache Partitioning for Tile-based Chip Multiprocessors. - Nadja Holtryd; Madhavan Manivannan; Per Stenström; Miquel Pericàs (IPDPS, 2020)

Coordinated Management of Processor Configuration and Cache Partitioning to Optimize Energy under QoS Constraints. - Mehrzad Nejat; Madhavan Manivannan; Miquel Pericàs; Per Stenström (IPDPS, 2020)

Coordinated management of DVFS and cache partitioning under QoS constraints to save energy in multi-core systems. - Mehrzad Nejat; Madhavan Manivannan; Miquel Pericàs; Per Stenström (J. Parallel Distributed Comput., 2020)

CBP: Coordinated management of cache partitioning, bandwidth partitioning and prefetch throttling. - Nadja Ramhöj Holtryd; Madhavan Manivannan; Per Stenström; Miquel Pericàs (PACT, 2021)

STEER: Asymmetry-aware Energy Efficient Task Scheduler for Cluster-based Multicore Architectures. - Jing Chen 038; Madhavan Manivannan; Bhavishya Goel; Mustafa Abduljabbar; Miquel Pericàs (SBAC-PAD, 2022)

ERASE: Energy Efficient Task Mapping and Resource Management for Work Stealing Runtimes. - Jing Chen 038; Madhavan Manivannan; Mustafa Abduljabbar; Miquel Pericàs (ACM Trans. Archit. Code Optim., 2022)

Cooperative Slack Management: Saving Energy of Multicore Processors by Trading Performance Slack Between QoS-Constrained Applications. - Mehrzad Nejat; Madhavan Manivannan; Miquel Pericàs; Per Stenström (ACM Trans. Archit. Code Optim., 2022)

eProcessor: European, Extendable, Energy-Efficient, Extreme-Scale, Extensible, Processor Ecosystem. - Lluc Alvarez; Abraham Ruiz; Arnau Bigas-Soldevilla; Pavel Kuroedov; Alberto González 004; Hamsika Mahale; Noe Bustamante; Albert Aguilera; Francesco Minervini; Javier Salamero; Oscar Palomar; Vassilis Papaefstathiou; et al. (CF, 2023)

SoK: Analysis of Root Causes and Defense Strategies for Attacks on Microarchitectural Optimizations. - Nadja Ramhöj Holtryd; Madhavan Manivannan; Per Stenström (EuroS&P, 2023)

SCALE: Secure and Scalable Cache Partitioning. - Nadja Ramhöj Holtryd; Madhavan Manivannan; Per Stenström (HOST, 2023)

JOSS: Joint Exploration of CPU-Memory DVFS and Task Scheduling for Energy Efficiency. - Jing Chen 038; Madhavan Manivannan; Bhavishya Goel; Miquel Pericàs (ICPP, 2023)

JOSS: Joint Exploration of CPU-Memory DVFS and Task Scheduling for Energy Efficiency. - Jing Chen; Madhavan Manivannan; Bhavishya Goel; Miquel Pericàs (CoRR, 2023)

Approx-RM: Reducing Energy on Heterogeneous Multicore Processors under Accuracy and Timing Constraints. - Muhammad Waqar Azhar; Madhavan Manivannan; Per Stenström (ACM Trans. Archit. Code Optim., 2023)

SWEEP: Adaptive Task Scheduling for Exploring Energy Performance Trade-offs. - Jing Chen 038; Madhavan Manivannan; Bhavishya Goel; Miquel Pericàs (IPDPS, 2024)