Effect of Noise on Analog Circuit Testing. - Madhu K. Iyer; Michael L. Bushnell (J. Electron. Test., 1999)

A Self-Test Methodology for IP Cores in Bus-Based Programmable SoCs. - Jing-Reng Huang; Madhu K. Iyer; Kwang-Ting Cheng (VTS, 2001)

Combining ATPG and Symbolic Simulation for Efficient Validation of Embedded Array Systems. - Ganapathy Parthasarathy; Madhu K. Iyer; Tao Feng 012; Li-C. Wang; Kwang-Ting Cheng; Magdy S. Abadir (ITC, 2002)

Software-Based Weighted Random Testing for IP Cores in Bus-Based Programmable SoCs. - Madhu K. Iyer; Kwang-Ting Cheng (VTS, 2002)

A comparison of BDDs, BMC, and sequential SAT for model checking. - Ganapathy Parthasarathy; Madhu K. Iyer; Kwang-Ting Cheng; Li-C. Wang (HLDVT, 2003)

SATORI - A Fast Sequential SAT Engine for Circuits. - Madhu K. Iyer; Ganapathy Parthasarathy; Kwang-Ting Cheng (ICCAD, 2003)

Efficient reachability checking using sequential SAT. - Ganapathy Parthasarathy; Madhu K. Iyer; Kwang-Ting Cheng; Li-C. Wang (ASP-DAC, 2004)

An efficient finite-domain constraint solver for circuits. - Ganapathy Parthasarathy; Madhu K. Iyer; Kwang-Ting Cheng; Li-C. Wang (DAC, 2004)

Safety Property Verification Using Sequential SAT and Bounded Model Checking. - Ganapathy Parthasarathy; Madhu K. Iyer; Kwang-Ting Cheng; Li-C. Wang (IEEE Des. Test Comput., 2004)

Structural search for RTL with predicate learning. - Ganapathy Parthasarathy; Madhu K. Iyer; Kwang-Ting Cheng; Forrest Brewer (DAC, 2005)

Efficient Conflict-Based Learning in an RTL Circuit Constraint Solver. - Madhu K. Iyer; Ganapathy Parthasarathy; Kwang-Ting Cheng (DATE, 2005)

An Efficient Sequential SAT Solver With Improved Search Strategies. - Feng Lu 002; Madhu K. Iyer; Ganapathy Parthasarathy; Li-C. Wang; Kwang-Ting Cheng; Kuang-Chien Chen (DATE, 2005)

RTL SAT simplification by Boolean and interval arithmetic reasoning. - Ganapathy Parthasarathy; Madhu K. Iyer; Kwang-Ting Cheng; Forrest Brewer (ICCAD, 2005)