Universality Results for Some Variants of P Systems. - Madhu Mutyam; Kamala Krithivasan (WMP, 2000)

P Systems with Membrane Creation: Universality and Efficiency. - Madhu Mutyam; Kamala Krithivasan (MCU, 2001)

Complexity Issues in Rewriting P Systems. - Madhu Mutyam (DCFS, 2002)

A Survey of Some Variants of P Systems. - Madhu Mutyam; Kamala Krithivasan (WMC-CdeA, 2002)

Generalized normal form for rewriting P systems. - Madhu Mutyam; Kamala Krithivasan (Acta Informatica, 2002)

Improved Results about Universality of P systems. - Madhu Mutyam; Kamala Krithivasan (Bull. EATCS, 2002)

Contextual P Systems. - Kamala Krithivasan; Madhu Mutyam (Fundam. Informaticae, 2002)

A Note on Hybrid P Systems. - Madhu Mutyam; Kamala Krithivasan (Grammars, 2002)

On a class of P automata. - Madhu Mutyam; Kamala Krithivasan (Int. J. Comput. Math., 2003)

Probabilistic Rewriting P Systems. - Madhu Mutyam (Int. J. Found. Comput. Sci., 2003)

Some Variants in Communication of Parallel Communicating Pushdown Automata. - M. Sakthi Balan; Kamala Krithivasan; Madhu Mutyam (J. Autom. Lang. Comb., 2003)

Array-rewriting P systems. - Rodica Ceterchi; Madhu Mutyam; Gheorghe Paun; K. G. Subramanian 001 (Nat. Comput., 2003)

Preventing Crosstalk Delay using Fibonacci Representation. - Madhu Mutyam (VLSI Design, 2004)

A Bus Encoding Technique for Power and Cross-talk Minimization. - P. Subrahmanya; R. Manimegalai; V. Kamakoti 001; Madhu Mutyam (VLSI Design, 2004)

Descriptional Complexity of Rewriting P Systems. - Madhu Mutyam (J. Autom. Lang. Comb., 2004)

Length Synchronization Context-Free Grammars. - Madhu Mutyam; Kamala Krithivasan (J. Autom. Lang. Comb., 2004)

Rewriting Tissue P Systems. - Madhu Mutyam; Vaka Jaya Prakash; Kamala Krithivasan (J. Univers. Comput. Sci., 2004)

On Characterizing Recursively Enumerable Languages by Insertion Grammars. - Madhu Mutyam; Kamala Krithivasan; A. Siddhartha Reddy (Fundam. Informaticae, 2005)

Rewriting P systems: improved hierarchies. - Madhu Mutyam (Theor. Comput. Sci., 2005)

Delay and peak power minimization for on-chip buses using temporal redundancy. - K. Najeeb; Vishal Gupta; V. Kamakoti 001; Madhu Mutyam (ACM Great Lakes Symposium on VLSI, 2006)

Delay and Energy Efficient Data Transmission for On-Chip Buses. - Madhu Mutyam; Melvin Eze; Narayanan Vijaykrishnan; Yuan Xie 001 (ISVLSI, 2006)

Compiler-directed thermal management for VLIW functional units. - Madhu Mutyam; Feihui Li; Narayanan Vijaykrishnan; Mahmut T. Kandemir; Mary Jane Irwin (LCTES, 2006)

Temporal Redundancy Based Encoding Technique for Peak Power and Delay Reduction of On-Chip Buses. - K. Najeeb; Vishal Gupta; V. Kamakoti 001; Madhu Mutyam (J. Low Power Electron., 2006)

Working with process variation aware caches. - Madhu Mutyam; Narayanan Vijaykrishnan (DATE, 2007)

Selective shielding: a crosstalk-free bus encoding technique. - Madhu Mutyam (ICCAD, 2007)

Variation Analysis of CAM Cells. - Amol Mupid; Madhu Mutyam; Narayanan Vijaykrishnan; Yuan Xie 001; Mary Jane Irwin (ISQED, 2007)

Investigating Simple Low Latency Reliable Multiported Register Files. - Andrew J. Ricketts; Madhu Mutyam; Narayanan Vijaykrishnan; Mary Jane Irwin (ISVLSI, 2007)

Exploiting on-chip data behavior for delay minimization. - Nallamothu Satyanarayana; Madhu Mutyam; A. Vinaya Babu (SLIP, 2007)

Block remap with turnoff: A variation-tolerant cache design technique. - Mohammed Abid Hussain; Madhu Mutyam (ASP-DAC, 2008)

Process Variation Aware Issue Queue Design. - Kanakagiri Raghavendra; Madhu Mutyam (DATE, 2008)

Power management of variation aware chip multiprocessors. - Abu Saad Papa; Madhu Mutyam (ACM Great Lakes Symposium on VLSI, 2008)

Word-interleaved cache: an energy efficient data cache architecture. - T. Venkata Kalyan; Madhu Mutyam (ISLPED, 2008)

Exploiting Variable Cycle Transmission for Energy-Efficient On-Chip Interconnect Design. - T. Venkata Kalyan; Madhu Mutyam; Vijaya Sankara Rao Pasupureddi (VLSI Design, 2008)

Delay-efficient bus encoding techniques. - Nallamothu Satyanarayana; A. Vinaya Babu; Madhu Mutyam (Microprocess. Microsystems, 2009)

Process-Variation-Aware Adaptive Cache Architecture and Management. - Madhu Mutyam; Feng Wang 004; Krishnan Ramakrishnan; Vijaykrishnan Narayanan; Mahmut T. Kandemir; Yuan Xie 001; Mary Jane Irwin (IEEE Trans. Computers, 2009)

Selective shielding technique to eliminate crosstalk transitions. - Madhu Mutyam (ACM Trans. Design Autom. Electr. Syst., 2009)

BOFAR: buffer occupancy factor based adaptive router for mesh NoCs. - John Jose; J. Shiva Shankar; K. V. Mahathi; Damarla Kranthi Kumar; Madhu Mutyam (NoCArc@MICRO, 2011)

Prevention flow-control for low latency torus networks-on-chip. - Arpit Joshi; Madhu Mutyam (NOCS, 2011)

Timing variation-aware scheduling and resource binding in high-level synthesis. - Kartikey Mittal; Arpit Joshi; Madhu Mutyam (ACM Trans. Design Autom. Electr. Syst., 2011)

SkipCache: miss-rate aware cache management. - Kanakagiri Raghavendra; Tripti S. Warrier; Madhu Mutyam (PACT, 2012)

TRACKER: A low overhead adaptive NoC router with load balancing selection strategy. - John Jose; K. V. Mahathi; J. Shiva Shankar; Madhu Mutyam (ICCAD, 2012)

Way Sharing Set Associative Cache Architecture. - C. J. Janraj; T. Venkata Kalyan; Tripti S. Warrier; Madhu Mutyam (VLSI Design, 2012)

Fibonacci Codes for Crosstalk Avoidance. - Madhu Mutyam (IEEE Trans. Very Large Scale Integr. Syst., 2012)

An Application-Aware Cache Replacement Policy for Last-Level Caches. - Tripti S. Warrier; B. Anupama; Madhu Mutyam (ARCS, 2013)

DeBAR: deflection based adaptive router with minimal buffering. - John Jose; Bhawna Nayak; Damarla Kranthi Kumar; Madhu Mutyam (DATE, 2013)

SLIDER: Smart Late Injection DEflection Router for mesh NoCs. - Bhawna Nayak; John Jose; Madhu Mutyam (ICCD, 2013)

Prevention slot flow-control mechanism for low latency torus network-on-chip. - Arpit Joshi; Prasanna Venkatesh Rengasamy; Madhu Mutyam (IET Comput. Digit. Tech., 2013)

Data remapping for an energy efficient burst chop in DRAM memory systems. - Sudharsan Jagathrakshakan; Venkata Kalyan Tavva; Madhu Mutyam (PACT, 2014)

Scattered refresh: An alternative refresh mechanism to reduce refresh cycle time. - T. Venkata Kalyan; Ravi Kasha; Madhu Mutyam (ASP-DAC, 2014)

SAMO: store aware memory optimizations. - Kanakagiri Raghavendra; Tripti S. Warrier; Madhu Mutyam (Conf. Computing Frontiers, 2014)

Minimally buffered single-cycle deflection router. - Gnaneswara Rao Jonna; John Jose; Rachana Radhakrishnan; Madhu Mutyam (DATE, 2014)

SFFMap: Set-First Fill mapping for an energy efficient pipelined data cache. - Pritam Majumder; T. Venkata Kalyan; Madhu Mutyam (ICCD, 2014)

Using packet information for efficient communication in NoCs. - Prasanna Venkatesh Rengasamy; Madhu Mutyam (NOCS, 2014)

EFGR: An Enhanced Fine Granularity Refresh Feature for High-Performance DDR4 DRAM Devices. - Venkata Kalyan Tavva; Ravi Kasha; Madhu Mutyam (ACM Trans. Archit. Code Optim., 2014)

Implementation and Analysis of History-Based Output Channel Selection Strategies for Adaptive Routers in Mesh NoCs. - John Jose; Madhu Mutyam (ACM Trans. Design Autom. Electr. Syst., 2014)

SkipCache: application aware cache management for chip multi-processors. - Tripti S. Warrier; Kanakagiri Raghavendra; Madhu Mutyam (IET Comput. Digit. Tech., 2015)

CASCADE: Congestion Aware Switchable Cycle Adaptive Deflection Router. - Gnaneswara Rao Jonna; Vamana Murthi Thuniki; Madhu Mutyam (ARCS, 2016)

PBC: Prefetched Blocks Compaction. - Kanakagiri Raghavendra; Biswabandan Panda; Madhu Mutyam (IEEE Trans. Computers, 2016)

FatCBST: Concurrent Binary Search Tree with Fatnodes. - Praveen Alapati; Venkata Kalyan Tavva; Madhu Mutyam (HPCC/SmartCity/DSS, 2017)

Concurrent Treaps. - Praveen Alapati; Swamy Saranam; Madhu Mutyam (ICA3PP, 2017)

RCTP: Region Correlated Temporal Prefetcher. - Dennis Antony Varkey; Biswabandan Panda; Madhu Mutyam (ICCD, 2017)

An Experimental Study on Dynamic Bank Partitioning of DRAM in Chip Multiprocessors. - Debiprasanna Sahoo; Manoranjan Satpathy; Madhu Mutyam (VLSID, 2017)

MBZip: Multiblock Data Compression. - Kanakagiri Raghavendra; Biswabandan Panda; Madhu Mutyam (ACM Trans. Archit. Code Optim., 2017)

CAMO: A novel cache management organization for GPGPUs. - Debiprasanna Sahoo; Swaraj Sha; Manoranjan Satpathy; Madhu Mutyam; Laxmi Narayan Bhuyan (ASP-DAC, 2018)

TDC: Tagless DRAM Cache. - S. R. Swamy Saranam; Madhu Mutyam (ISVLSI, 2018)

ReDRAM: A Reconfigurable DRAM Cache for GPGPUs. - Debiprasanna Sahoo; Swaraj Sha; Manoranjan Satpathy; Madhu Mutyam (IEEE Comput. Archit. Lett., 2018)

Formal Modeling and Verification of Controllers for a Family of DRAM Caches. - Debiprasanna Sahoo; Swaraj Sha; Manoranjan Satpathy; Madhu Mutyam; S. Ramesh 002; Partha S. Roop (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018)

POSTER: Variable Sized Cache-Block Compaction. - Sayantan Ray; Madhu Mutyam (PACT, 2019)

Post-Model Validation of Victim DRAM Caches. - Debiprasanna Sahoo; Shivani Tripathy; Manoranjan Satpathy; Madhu Mutyam (ICCD, 2019)

Endurance enhancement of write-optimized STT-RAM caches. - Puneet Saraf; Madhu Mutyam (MEMSYS, 2019)

Formal Modeling and Verification of a Victim DRAM Cache. - Debiprasanna Sahoo; Swaraj Sha; Manoranjan Satpathy; Madhu Mutyam; S. Ramesh 002; Partha S. Roop (ACM Trans. Design Autom. Electr. Syst., 2019)

Router Buffer Caching for Managing Shared Cache Blocks in Tiled Multi-Core Processors. - Joe Augustine; Kanakagiri Raghavendra; John Jose; Madhu Mutyam (ICCD, 2020)

Fuzzy fairness controller for NVMe SSDs. - Shivani Tripathy; Debiprasanna Sahoo; Manoranjan Satpathy; Madhu Mutyam (ICS, 2020)

Concurrent Treaps and Impact of Locking Objects. - Praveen Alapati; Madhu Mutyam; Swamy Saranam (New Gener. Comput., 2020)

Optimization of Intercache Traffic Entanglement in Tagless Caches With Tiling Opportunities. - S. R. Swamy Saranam Chongala; Sumitha George; Hariram Thirucherai Govindarajan; Jagadish Kotra; Madhu Mutyam; John Sampson; Mahmut T. Kandemir; Vijaykrishnan Narayanan (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

A Scalable and Energy-Efficient Concurrent Binary Search Tree With Fatnodes. - Praveen Alapati; Venkata Kalyan Tavva; Madhu Mutyam (IEEE Trans. Sustain. Comput., 2020)

Formal Modeling and Verification of Security Properties of a Ransomware-Resistant SSD. - Shivani Tripathy; Debiprasanna Sahoo; Manoranjan Satpathy; Madhu Mutyam (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

Cache Line Pinning for Mitigating Row Hammer Attack. - Praseetha M; Madhu Mutyam; Venkata Kalyan Tavva (ICPP, 2024)

Selective Memory Compression for GPU Memory Oversubscription Management. - Abdun Nihaal; Madhu Mutyam (ICPP, 2024)