Genetic Algorithms in Hardware-Software Partitioning. - Madhura Purnaprajna; Marek Z. Reformat; Witold Pedrycz (ERSA, 2004)

Genetic algorithms for hardware-software partitioning and optimal resource allocation. - Madhura Purnaprajna; Marek Z. Reformat; Witold Pedrycz (J. Syst. Archit., 2007)

Power Aware Reconfigurable Multiprocessor for Elliptic Curve Cryptography. - Madhura Purnaprajna; Christoph Puttmann; Mario Porrmann (DATE, 2008)

Self-optimization of MPSoCs Targeting Resource Efficiency and Fault Tolerance. - Mario Porrmann; Madhura Purnaprajna; Christoph Puttmann (AHS, 2009)

Using Run-time Reconfiguration for Energy Savings in Parallel Data Processing. - Madhura Purnaprajna; Christopher Pohl; Mario Porrmann; Ulrich Rückert 001 (ERSA, 2009)

Run-time reconfigurability in embedded multiprocessors. - Madhura Purnaprajna; Mario Porrmann; Ulrich Rückert 001 (SIGARCH Comput. Archit. News, 2009)

Runtime Reconfiguration of Multiprocessors Based on Compile-Time Analysis. - Madhura Purnaprajna; Mario Porrmann; Ulrich Rückert 001; Michael Hussmann; Michael Thies; Uwe Kastens (ACM Trans. Reconfigurable Technol. Syst., 2010)

Run-time reconfigurable multiprocessors. - Madhura Purnaprajna (2010)

Shortening Design Time through Multiplatform Simulations with a Portable OpenCL Golden-model: The LDPC Decoder Case. - Gabriel Falcão 001; Muhsen Owaida; David Novo; Madhura Purnaprajna; Nikolaos Bellas; Christos D. Antonopoulos; Georgios Karakonstantis; Andreas Burg 001; Paolo Ienne (FCCM, 2012)

Making wide-issue VLIW processors viable on FPGAs. - Madhura Purnaprajna; Paolo Ienne (ACM Trans. Archit. Code Optim., 2012)

A Case for Heterogeneous Technology-Mapping: Soft Versus Hard Multiplexers. - Madhura Purnaprajna; Paolo Ienne (FCCM, 2013)

Shadow AICs: reaping the benefits of and-inverter cones with minimal architectural impact (abstract only). - Hadi Parandeh-Afshar; Grace Zgheib; David Novo; Madhura Purnaprajna; Paolo Ienne (FPGA, 2013)

Shadow And-Inverter Cones. - Hadi Parandeh-Afshar; Grace Zgheib; David Novo; Madhura Purnaprajna; Paolo Ienne (FPL, 2013)

Enabling seamless execution on hybrid CPU/FPGA systems: Challenges & directions. - Meena Belwal; Madhura Purnaprajna; T. S. B. Sudarshan (FPL, 2015)

Enhancing Design Space Exploration by Extending CPU/GPU Specifications onto FPGAs. - Muhsen Owaida; Gabriel Falcão 001; João Andrade; Christos D. Antonopoulos; Nikolaos Bellas; Madhura Purnaprajna; David Novo; Georgios Karakonstantis; Andreas Burg 001; Paolo Ienne (ACM Trans. Embed. Comput. Syst., 2015)

Performance modeling for data distribution in heterogeneous computing systems: work in progress. - Vanishree K; Madhura Purnaprajna (CASES, 2018)

Streaming Tiles: Flexible Implementation of Convolution Neural Networks Inference on Manycore Architectures. - Nesma M. Rezk; Madhura Purnaprajna; Zain Ul-Abdin (IPDPS Workshops, 2018)

TileNET: Scalable Architecture for High-Throughput Ternary Convolution Neural Networks Using FPGAs. - Sahu Sai Vikram; Vibha Panty; Mihir Mody; Madhura Purnaprajna (VLSID, 2018)

k-Core: Hardware Accelerator for k-Mer Generation and Counting used in Computational Genomics. - Simmi M. Bose; Varsha S. Lalapura; S. Saravanan; Madhura Purnaprajna (VLSID, 2019)

Gbit/s Non-Binary LDPC Decoders: High-Throughput using High-Level Specifications. - Oscar Ferraz; Srinivasan Subramaniyan; Guohui Wang; Joseph R. Cavallaro; Gabriel Falcão 001; Madhura Purnaprajna (FCCM, 2020)

Pushing the Limits of Energy Efficiency for Non-Binary LDPC Decoders on GPUs and FPGAs. - Srinivasan Subramaniyan; Oscar Ferraz; M. R. Ashuthosh; Santosh Krishna; Guohui Wang; Joseph R. Cavallaro; Vítor Silva 001; Gabriel Falcão 001; Madhura Purnaprajna (SiPS, 2020)

Recurrent Neural Networks: An Embedded Computing Perspective. - Nesma M. Rezk; Madhura Purnaprajna; Tomas Nordström; Zain Ul-Abdin (IEEE Access, 2020)

Demystifying Compression Techniques in CNNs: CPU, GPU and FPGA cross-platform analysis. - Remya Ramakrishnan; Aditya K. V. Dev; Darshik A. S; Renuka Chinchwadkar; Madhura Purnaprajna (VLSID, 2021)

TileNET: Hardware accelerator for ternary Convolutional Neural Networks. - Sagar Eetha; Sruthi P. K.; Vibha Panty; Sahu Sai Vikram; Mihir Mody; Madhura Purnaprajna (Microprocess. Microsystems, 2021)

MAPPARAT: A Resource Constrained FPGA-Based Accelerator for Sparse-Dense Matrix Multiplication. - M. R. Ashuthosh; Santosh Krishna; Vishvas Sudarshan; Srinivasan Subramaniyan; Madhura Purnaprajna (VLSID, 2022)

A Survey on High-Throughput Non-Binary LDPC Decoders: ASIC, FPGA, and GPU Architectures. - Oscar Ferraz; Srinivasan Subramaniyan; Ramesh Chinthala; João Andrade; Joseph R. Cavallaro; Soumitra Kumar Nandy; Vítor Silva 001; Xinmiao Zhang 001; Madhura Purnaprajna; Gabriel Falcão 001 (IEEE Commun. Surv. Tutorials, 2022)

Enabling High-Level Design Strategies for High-Throughput and Low-Power NB-LDPC Decoders. - Srinivasan Subramaniyan; Oscar Ferraz; M. R. Ashuthosh; Santosh Krishna; Guohui Wang; Joseph R. Cavallaro; Vítor Silva 001; Gabriel Falcão 001; Madhura Purnaprajna (IEEE Des. Test, 2023)

Optimization of Sub-Threshold Standard Cells for Energy Efficient Designs. - Vardhan Suroshi; Karthik B. K; Vikram Kannur; Vinay Reddy; Madhura Purnaprajna (VLSID, 2025)