Hierarchical temporal memory implementation on FPGA using LFSR based spatial pooler address space generator. - Madis Kerner; Kalle Tammemäe (DDECS, 2017)

An Efficient FPGA-based Architecture for Contractive Autoencoders. - Madis Kerner; Kalle Tammemäe; Jaan Raik; Thomas Hollstein (FCCM, 2020)

Triple Fixed-Point MAC Unit for Deep Learning. - Madis Kerner; Kalle Tammemäe; Jaan Raik; Thomas Hollstein (DATE, 2021)