Extended RISC-V hardware architecture for future digital communication systems. - Maël Tourres; Cyrille Chavet; Bertrand Le Gal; Jérémie Crenne; Philippe Coussy (5GWF, 2021)

Specialized Scalar and SIMD Instructions for Error Correction Codes Decoding on RISC-V Processors. - Maël Tourres; Cyrille Chavet; Bertrand Le Gal; Philippe Coussy (IEEE Access, 2025)